A power and ground plane separation of 0.254 mm (0.010 in.) results in approximately 100 pF/in
2
, while a
separation of 0.102 mm (0.004 in.) provides approximately 200 pF/in
2
. Plane capacitors provide other
important benefits,
such as
a low-impedance path for AC return currents, in cases where a given
reference plane has a discontinuity.
As for discrete capacitors, the footprint and physical size of discrete capacitors have a significant effect on
the frequencies at which the capacitors provide effective de-coupling. To minimize series inductance, use
smaller-packaged ceramic capacitors (
such as
0402 or 0201) for mid-ranged frequency de-coupling (20 to
250 MHz). Use a mixed selection of capacitor values,
such as
0.1 and 0.01 µF, to lower the impedance
across a wide frequency range.
Capacitor footprint layout is important in determining the frequencies at which they are effective. Avoid
adding trace segments from the capacitor pads to the vias. These segments add more series inductance,
thereby lowering the discrete capacitor LC resonant frequency. Place the vias tangentially to the
capacitor pads, and if possible, add multiple vias per pad. (Refer to
Right the First Time: A Practical
Handbook on High Speed PCB and System Design,
by Lee Ritchie.) If a plane capacitor is used, the
placement of small discrete capacitors is not critical. Place the capacitors on the solder side of the board,
under the Ball Grid Array (BGA) footprint (in the solder ball void area), and directly outside the BGA matrix.
If a plane capacitor is not possible (this is typically the case for 4- and 6-layer boards), place the
capacitors as close to the balls as possible. If a PCB layer stackup is such that plane capacitors are not
possible, add power or ground fill areas on the signal layers, as follows:
If a signal layer is referencing a DC ground plane, fill with power
If a signal layer is referencing a DC power plane, fill with ground
These copper fill areas tie to the main power and ground planes, through the component balls.
Multi-layer ceramic chip capacitors (
such as
10 to 22 µF) can be used for bulk de-coupling of
lower-frequency components. The proximity of these capacitors is not critical; therefore, they can be
placed outside the BGA matrix.
It is strongly recommended to measure the attenuation-versus-frequency profile of each power rail, on a
completed board that is loaded only with bypass capacitors. This serves to confirm that there are no
attenuation holes in the power-de-coupling design.
illustrates examples of how various footprints for 0603-size capacitors can change
series inductance.
Figure 13. Capacitor Footprint Effects on Series Inductance
PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
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© 2007 PLX Technology, Inc. All Rights Reserved.
