PLL1
CDR1
PLL2
CDR2
RefClk
Rx1
Rx2
Tx1
Tx2
Channel
Channel
Device 1
Device 2
T1
T2
T3
T4
T5
Transport Delay Delta = (T1+T2+T3) – (T4+T5) < 12 ns
Figure 3. Transport Delay Delta
Figure 4. PEX 8632 RefClk Circuitry
1.1.4
Channel
In PCI Express, the Channel refers to the board level copper interconnects (including connectors) that lie
between the Transmitter and Receiver balls. The Channel is represented as a transmission line, which
can be modeled by a distributed series of Resistance Inductance Conductance Capacitance (RLGC)
circuits. A transmission line behaves like a low-pass filter, due to frequency-dependent dielectric and
conductor losses.
In PCI Express, the Channel contributes to amplitude loss and deterministic jitter. It is important to
minimize discontinuities,
such as
vias and stubs, to minimize Channel effects.
A common issue that presents itself to PCI Express system designers is determining allowable Channel
length. This is a question that does not have a simple answer. The best way to determine whether a
particular Channel length is allowable is to simulate the Channel, using PLX-provided HSPICE models.
The
PCI Express Base Specification, Revision 2.0,
provides additional details for simulating a Channel.
PEX 8632-AA Quick Start Hardware Design Guide, Version 1.1
© 2007 PLX Technology, Inc. All Rights Reserved.
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