Pleora Technologies iPort NTx-Pro, Hardware Manual, Page: 49 / 52

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Copyright © 2010 Pleora Technologies Inc.
Camera Link Pixel Bus Definitions
Pixel Bus Definitions
The Camera Link Standard defines the bit assignments for various pixel types. For your reference, the
table below lists the Camera Link ports and the associated IP Engine signal names.
Camera Link Pixel Bus Definitions
Signal Name
a
a. For all A/B, or R/G/B signals, 0 denotes the least significant bit (e.g. A0) on the IP Engine. If your camera uses 0 as the MSB, you must
reverse the cabling. Port A denotes the primary image; port B, the secondary. Use port B as the second tap for two-tap cameras.
PIXEL_DATA0 Port A0 A0 A0 A0 A0 A0 R0
PIXEL_DATA1 Port A1 A1 A1 A1 A1 A1 R1
PIXEL_DATA2 Port A2 A2 A2 A2 A2 A2 R2
PIXEL_DATA3 Port A3 A3 A3 A3 A3 A3 R3
PIXEL_DATA4 Port A4 A4 A4 A4 A4 A4 R4
PIXEL_DATA5 Port A5 A5 A5 A5 A5 A5 R5
PIXEL_DATA6 Port A6 A6 A6 A6 A6 A6 R6
PIXEL_DATA7 Port A7 A7 A7 A7 A7 A7 R7
PIXEL_DATA8 Port B0 B0 A8 A8 A8 A8 G0
PIXEL_DATA9 Port B1 B1 A9 A9 A9 A9 G1
PIXEL_DATA10 Port B2 B2 Reserved A10 A10 A10 G2
PIXEL_DATA11 Port B3 B3 Reserved A11 A11 A11 G3
PIXEL_DATA12 Port B4 B4 B8 B8 A12 A12 G4
PIXEL_DATA13 Port B5 B5 B9 B9 A13 A13 G5
PIXEL_DATA14 Port B6 B6 Reserved B10 Reserved A14 G6
PIXEL_DATA15 Port B7 B7 Reserved B11 Reserved A15 G7
PIXEL_DATA16 Port C0 Reserved B0 B0 Reserved Reserved B0
PIXEL_DATA17 Port C1 Reserved B1 B1 Reserved Reserved B1
PIXEL_DATA18 Port C2 Reserved B2 B2 Reserved Reserved B2
PIXEL_DATA19 Port C3 Reserved B3 B3 Reserved Reserved B3
PIXEL_DATA20 Port C4 Reserved B4 B4 Reserved Reserved B4
PIXEL_DATA21 Port C5 Reserved B5 B5 Reserved Reserved B5
PIXEL_DATA22 Port C6 Reserved B6 B6 Reserved Reserved B6
PIXEL_DATA23 Port C7 Reserved B7 B7 Reserved Reserved B7
8-bit 10-bit
12-bit
14-bit 16-bit Port 24-bit RGB