Pleora Technologies iPort NTx-Pro, Hardware Manual, Page: 26 / 52

22 Connector: User Circuitry: 2x 50-pin FFC/FPC
Copyright © 2010 Pleora Technologies Inc.
Signal Names: (J5) 50-Pin FFC/FPC - Detail
The table below contains detailed descriptions of the signal names for the (J5) 50-Pin FFC/FPC that
supplies user signals to the NTx-Pro IP Engine.
Signal Names: (J5) 50-Pin FFC/FPC - Detail
Name Pin No. Type Level Description
3.3V 1, 2, 3 Power Output 3.3V 3.3V power output to user circuitry.
The current limitation is 0.4A for
each pin; 1.0A in total.
PWR_ON_RST# 6 Open Drain, I/O 2.5V A power-on reset (POR) from the
NTx-Pro. This is an open drain
signal pulled up to 2.5V on the
NTx-Pro board.
FPGA_SEL0-1 49, 50 Input 2.5V FGPA load selection pins. Defines
the FPGA load type on power-up.
There are two 470K pull-down
resistors on these signals. Both the
FPGA main load and backup load
have an internal weak (but, greater
than 470K) pull-up enabled by
default. If these pins remain uncon-
nected, the main load is selected.
For improved noise immunity,
these pins must remain connected
through a 1Kohm or less (e.g., 0
ohm) resistor to maintain a logical
0 or 1 (2.5V). Refer to the section,
“FPGA Selection Pins” on page 24
for the circuit configuration and
jumper pins to select the main and
backup loads.
The backup load is selected when
FPGA_SEL0 and FPGA_SEL1 are
set to the logic low level.
The main load is selected when
FPGA_SEL0 and FPGA_SEL1 are
set to the logic high level.
2.5V signals, but can be pulled up
to static 3.3V signals.
Other combinations are reserved for
future use.
GND 4, 9, 18,
27, 36, 45 Ground Ground
SYSTEM_CLK 5 Output 2.5V 2.5V 33.33300 MHz +/- 50ppm
system clock generator.
IO33_PLL_P0 7 Output 3.3V Camera Control 3
IO33_PLL_N0 8 Output 3.3V Camera Control 4