Pleora Technologies iPORT CL-Ten, User Manual, Page: 27 / 72

23 Programmable Logic Controller (PLC)
Input Debouncing Block
The input debouncing block filters spurious transitions from input signals. Each input signal can be
independently configured to hold signal transitions between 480 ns and ~31 ms. While holding the first
transition, the input debouncing block ignores further transitions for the configured duration.
The hold times can be configured in increments of 480 ns (16 cycles of the video interface system clock).
Setting the hold value to 0 disables the input debouncing block for that input signal.
Hold time = Hold value * 480 ns
Input Synchronization Block
The synchronization block samples input signals in time with the video interface system clock. The
system clock has a 30 ns period (33 MHz clock cycle). To maximize stability of the input signals and
minimize the risk of meta-stability problems, the synchronization block uses two consecutive flip-flops.
The synchronization block latches the input on every rising edge of the system clock.