XV-DVR9H
173
5
7
8
5
6
7
8
C
D
F
A
B
E
(a) Flash ROM interface pins
(6) External ROM connection pins
No.
Pin Name
I/O
Function
Active
196, 194-189,
186-178
D [15 : 0]
I/O
External ROM data bus
Data bus in the external ROM access.
Process of pull-up or pull down is necessary.
−
175, 174, 172,
171, 169-167,
165-156
A [17 : 1]
O
External ROM address bus
Address bus in the external ROM access.
Can addressing the 256k byte space.
−
176
RDZ
O
ROM read
Strobe signal which shows a read cycle for external ROM.
It becomes the inactive in the idle state.
L
177
WRZ
O
ROM write
Strobe signal which shows a write cycle for external ROM.
L
(b) EEPROM interface pins
No.
Pin Name
I/O
Function
Active
145
SO
I/O
Serial transmit data output of clock-synchronous system serial interface (CSI)
−
146
SI
I/O
Serial receive data input of clock-synchronous system serial interface (CSI)
−
147
SCK
I/O
Clock output of clock-synchronous system serial interface (CSI)
−
151
SCS
I/O
Chip select output of clock-synchronous system serial interface (CSI)
−
(7) Clock and reset pins
No.
Pin Name
I/O
Function
Active
1
RESETB
I
Reset
RESETB input is asynchronous input. When a signal of fixed low-level width is input
without relation to an operation clock, take precedence of all operation, and reset the
system. Note: RESETB is low-active.
L
202
HS_CLK
I
Host clock
Clock input pin which is supplied to CPU core and built-in peripheral I/O.
Please input 27 MHz clock. Perform 2 multiply with internal PLL by 27 MHz clock, 54
MHz clock is supplied to CPU core and internal peripheral I/O.
−
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