XV-DVR9H
171
5
7
8
5
6
7
8
C
D
F
A
B
E
(3) Audio interface pins
No.
Pin Name
I/O
Function
Active
104
AMCLK48
I
Audio master clock input for sampling frequency 48 kHz
−
103
AMCLK44
I
Audio master clock input for sampling frequency 44 kHz
−
101
AMCLKO
O
Audio master clock output
−
96
PCM1
I/O
Audio PCM serial data
At 2ch : System 1 (data of audio block 1)
At 4ch : System 1
The above is default setting value. Input/output data of PCM 1 and PCM 2 is replaced
by Channel swap setting of an AUDIO_FUNC register.
−
97
PCM2
I/O
Audio PCM serial data
At 2ch : Mute
At 4ch : System 2 (data of audio block 2)
The above is default setting value. Input/output data of PCM 1 and PCM 2 is replaced
by Channel swap setting of an AUDIO_FUNC register.
Note: Cannot use it in DV decode.
−
98
AEMP1
O
PCM1 emphasis ON/OFF in PCM 1 output
H
93
ALRCK
I/O
Audio LR clock
L ch : High
R ch : Low
−
94
ABCK
I/O
Audio bit clock
−
49, 48
AFS [2 : 1]
O
Audio sampling frequency
AFS2 AFS1
44.1 kHz
0
1
48 kHz
0
0
32 kHz
1
0
−
102
APWM
O
PWM signal for audio PLL
−
(4) SDRAM interface pins
No.
Pin Name
I/O
Function
Active
77
MCLK
O
CLK pin connection of SDRAM
−
76
MRAS
O
RAS pin connection of SDRAM
−
75
MCAS
O
CAS pin connection of SDRAM
−
74
MWE
O
WE pin connection of SDRAM
−
92, 90-83,
81-79
MA [ 11 : 0]
O
Address pin connection of SDRAM
−
I/O
Data pin connection of SDRAM
Note: Process of pull-up or pull down is necessary.
So connect it to SDRAM directly.
−
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