XV-DVR9H
167
5
7
8
5
6
7
8
C
D
F
A
B
E
• Control Pins
• IC
No.
Pin Name
I/O
Function
26
PC0
I
Power class set input
This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H.
IEEE1394a-2000 chapter [4.3.4.1]
27
PC1
I
28
PC2
I
30
CMC
I
Configuration manager capable setting
This pin status will be loaded to Contender bit which allocated to PHY register 4H.
0 : Non contender
1 : Contender
55
RESETB
I
Power on reset input
Connect to GND through a 0.1
µ
F capacitor.
0 : Reset
1 : Normal
61
SPD/BDB
I
FNSel = 0
Speed select (UPD72852GB)
0 : MAX. S200
1 : MAX. S400
O
FNSel = 1
BIAS Detected output (Logical Inverse)
0 : BIAS is coming from some port.
1 : BIAS is not coming from any port.
No.
Pin Name
I/O
Function
29, 51 IC (AL)
−
Internally Connected (Low Clamped)
Connected to GND.
3
IC (DL)
−
Internally Connected (Low Clamped)
Connected to GND.
• Power Supply Pins
No.
Pin Name
I/O
Function
25, 31, 40, 47, 54
AV
DD
−
Analog power
24, 33, 35, 42, 49, 52, 53
AGND
−
Analog GND
4, 10, 20, 56, 60
DV
DD
−
Digital V
DD
1, 7, 13, 16, 21, 57, 64
DGND
−
Digital GND
• Other Pins
No.
Pin Name
I/O
Function
41
TpBias0
O
Port 0 twisted pair output
O
Port 1 twisted pair output
−
Resistor connection pin 1 for reference current generator
Please connect to GND pin through the 9.1 k
Ω
resistor.
−
Crystal oscillator connection XI
−
Crystal oscillator connection XO
I
Function Select
0 : #61 acts as SPD (UPD72852GB compliant)
1 : #61 acts as BDB
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