PDP-507CMX
106
1
2
3
4
1
2
3
4
C
D
F
A
B
E
⇒
INPUT 3 or INPUT 4
(COMP / S1)
Failure in the MAIN Assy
Are the sync and clock signals
output from VSIF Assy ?
Waveform 29-1, 29-2
Are the sync and clock signals
input to pins 1, 2 and 4 of
CN6301?
Waveform 29-1, 29-2
Failure in the COMMSLOT IF
Asssy or flexible cable
Yes
Yes
Yes
Yes
Yes
Does not either of INPUT3 or
INPUT4 display?
No
Is the clock signal input to pin 2 of
IC6302?
Waveform 29-2
No
Failure in the VSIF Assy
No
Failure in the VSIF Assy
Is the clock signal input to pin 2 of
IC6304?
Waveform 29-1, 29-2
No
No
Are the sync and clock signals
input to pins 168, 169 and 172 of
IC6301?
Waveform 29-1, 29-2
Failure in the IC6301 and
peripheral parts
Failure in the IC6304 and
peripheral parts
No
Failure in the IC6302 and
peripheral parts
No
Summary of Contents for PDP 507CMX
Page 44: ...PDP 507CMX 44 1 2 3 4 1 2 3 4 C D F A B E 4 2 OVERALL CONNECTION DIAGRAM 2 2 ...
Page 45: ...PDP 507CMX 45 5 6 7 8 5 6 7 8 C D F A B E ...
Page 84: ...PDP 507CMX 84 1 2 3 4 1 2 3 4 C D F A B E 500ns div 500ns div 200ns div ...
Page 104: ...PDP 507CMX 104 1 2 3 4 1 2 3 4 C D F A B E ...