23
PD-30-K
5
6
7
8
5
6
7
8
A
B
C
D
E
F
• Pin Function
Symbol
Type
Description
CLK
Input
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of
CLK. CLK also increments the internal burst counter and controls the output registers.
CKE
Input
Clock Enable:
CKE activates (HIGH) and deactivates (LO
W
) the CLK signal. If CKE goes low
synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains
low.
W
hen all banks are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes. CKE is synchronous except after the device enters Power Down and Self Refresh
modes, where CKE becomes asynchronous until exiting the same mode. The input buffers, including CLK,
are disabled during Power Down and Self Refresh modes, providing low standby power.
V
SS
Supply
BA1
BA0
Select Bank
0
0
BA
N
K #A
0
1
BA
N
K #B
1
0
BA
N
K #C
1
1
BA
N
K #D
Ground
V
DD
Supply
Power Supply:
+3.3
V
± 0.3
V
V
SSQ
Supply
DQ Ground:
Provide isolated ground to DQs for improved noise immunity. (0
V
)
V
DDQ
Supply
DQ Power:
Provide isolated power to DQs for improved noise immunity. (3.3
V
± 0.3
V
)
N
C/RFU
–
No Connect:
These pins should be left unconnected.
DQ0 - DQ15
Input/
Output
Data I/O:
The DQ0-15 input and output data are synchronized with the positive edges of CLK. The I/Os
are maskable during Reads and
W
rites.
LDQM, UDQM
Input
Data Input/Output Mask:
Controls output buffers in read mode and masks Input data in write mode.
W
E#
Input
Write Enable:
The
W
E# signal defines the operation commands in conjunction with the RAS# and CAS#
signals and is latched at the positive edges of CLK. The
W
E# input is used to select the BankActivate or
Precharge command and Read or
W
rite command.
CAS#
Input
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction with the
RAS# and
W
E# signals and is latched at the positive edges of CLK.
W
hen RAS# is held "HIGH" and CS#
is asserted "LO
W
," the column access is started by asserting CAS# "LO
W
." Then, the Read or
W
rite
command is selected by asserting
W
E# "LO
W
" or "HIGH."
RAS#
Input
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction with the CAS#
and
W
E# signals and is latched at the positive edges of CLK.
W
hen RAS# and CS# are asserted "LO
W
"
and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command is selected
by the
W
E# signal.
W
hen the
W
E# is asserted "HIGH," the BankActivate command is selected and the
bank designated by BA is turned on to the active state.
W
hen the
W
E# is asserted "LO
W
," the Precharge
command is selected and the bank designated by BA is switched to the idle state after the precharge
operation.
CS#
Input
Chip Select:
CS# enables (sampled LO
W
) and disables (sampled HIGH) the command decoder. All
commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on
systems with multiple banks. It is considered part of the command code.
A0 - A11
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row address A0-A11) and
Read/
W
rite command (column address A0-A7 with A10 defining Auto Precharge) to select one location
out of the 2M available in the respective bank. During a Precharge command, A10 is sampled to
determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-code
during a Mode Register Set command.
BA0, BA1
Input
Bank Activate:
BA0, BA1 input select the bank for operation.
