22
PD-30-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
SDRAM (64M)
• Block Diagram
• Pin Arrangement
15
4
S
S
V
D
D
V
25
3
5
1
Q
D
0
Q
D
35
2
Q
S
S
V
Q
D
D
V
45
1
4
1
Q
D
1
Q
D
55
0
3
1
Q
D
2
Q
D
64
9
Q
D
D
V
Q
S
S
V
74
8
2
1
Q
D
3
Q
D
84
7
1
1
Q
D
4
Q
D
94
6
Q
S
S
V
Q
D
D
V
10
45
0
1
Q
D
5
Q
D
11
44
9
Q
D
6
Q
D
12
43
Q
D
D
V
Q
S
S
V
13
42
8
Q
D
7
Q
D
14
41
S
S
V
D
D
V
15
40
U
F
R/
C
N
M
Q
D
L
16
39
M
Q
D
U
#
E
W
17
38
K
L
C
#
S
A
C
18
37
E
K
C
#
S
A
R
19
36
C
N
#
S
C
20
35
1
1
A
0
A
B
21
34
9
A
1
A
B
22
33
8
A
P
A/
0
1
A
23
32
7
A
0
A
24
31
6
A
1
A
25
30
5
A
2
A
26
29
4
A
3
A
27
28
S
S
V
D
D
V
CLK
CKE
CS#
RAS#
CAS#
WE#
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
REFRESH
COUNTER
DQ Buffer
1M x 16
CELL ARRAY
(BANK #A)
Row
Decoder
1M x 16
CELL ARRAY
(BANK #B)
Row
De
code
r
1M x 16
CELL ARRAY
(BANK #C)
Row
Decoder
1M x 16
CELL ARRAY
(BANK #D)
Ro
w
Decoder
Column Decoder
Column Decoder
Column Decoder
Column Decoder
MODE
REGISTER
A9
A11
BA0
BA1
~
A0
DQ15
DQ0
~
ADDRESS
BUFFER
A10/AP
LDQM, UDQM
IG2J08165G (EM638165TS-6G)(MAIN PCB ASSY: IC4002)
