20
PD-30-K
1
2
3
4
A
B
C
D
E
F
1
2
3
4
• Pin Function
Category
Pin Name
I/O
Function
Power supply
input
V
CC1,
V
CC2,
V
SS
I/O
Input 2.7
V
- 5.5
V
into
V
CC1,
V
CC2. The input condition is
V
CC1 =
V
CC2.
Input 0
V
into
V
SS.
Analog power supply
input
A
V
CC, A
V
SS
I
Power supply input of the A/D converter.
Connect A
V
CC to
V
CC1. Connect A
V
SS to
V
SS.
I
2
C mode
SDA0 - SDA2
I/O
Serial data input and output. (but the output of SDA2 is
N
channel open drain.)
SCL0 - SCL2
I/O
Transfer clock input and output. (but the output of SCL2 is
N
channel open drain.)
Serial interface
CTS0 - CTS2
I
Transmission system order input.
RTS0 - RTS2
O
Reception system order output.
CLK0 - CLK2
I/O
Transfer clock input and output.
RXD0 - RXD2
I
Serial data input.
TXD0 - TXD2
O
Serial data output. (but the output of TXD2 is
N
channel open drain.)
CLKS1
O
Output of the transfer clock plural terminal output function.
Timer B
TB0I
N
- TB2I
N
I
Timer B0 - B2 input.
Timer A
TA0OUT - TA2OUT
I/O
Input and output of timer A0 - A2. (but the output of TA0OUT is
N
channel open drain.)
TA0I
N
- TA2I
N
I
Timer A0 - A2 input.
Key input interrupt input
KI0 - KI3
I
Input of the key input interrupt.
N
MI interrupt input
N
MI
I
Input of the
N
MI interrupt.
I
N
T interrupt input
I
N
T0 - I
N
T4
I
Input of the I
N
T interrupt.
Clock output
CLKOUT
O
Output the clock of the period same as fc, f
8
or f32.
Main clock input
XI
N
I
Main clock output
XOUT
O
Input and output terminals of the main clock oscillation circuit. Connect a ceramic
resonator or a crystal oscillation child between XI
N
and XOUT.
W
hen you input a
clock formed outside, input a clock from XI
N
, and perform XOUT for open.
Sub clock input
XCI
N
I
Sub clock output
XCOUT
O
Input and output terminals of the subclock oscillation circuit. Connect a crystal
oscillation child between XCI
N
and XCOUT.
W
hen you input a clock formed outside,
input a clock from XCI
N
, and perform XCOUT for open.
ALE
O
Signals for a latch to do an address.
HOLD
I
The microcomputer becomes the hold state the input of this terminal during a period of "L".
W
RL/
W
R,
W
RH/BHE,
RD
O
Output
W
RL,
W
RH (
W
R, BHE), RD signals. Be changed
W
RL,
W
RH or BHE,
W
R by
a program.
· at
W
RL,
W
RH, RD selected
In case of external data bus is 16 bits,
W
RL signal is "L", writes it in the even
number address, and
W
RH signal is "L", writes it in the odd number address.
· at
W
R, BHE, RD selected
W
R signal is "L", writes. RD signal is "L", read. BHE signal is "L", accesses it by
an odd number house number.
Use this mode at the external data bus is
8
bits.
CS0 - CS3
O
Chip select signals. Use it for designation of the access space.
A0 - A19
O
Output address A0 - A19.
Bus control pin
D0 - D7
I/O
W
hen accessed the area selecting a separate bus, input and output data (D0 - D7).
D
8
- D15
I/O
W
hen an external data bus accessed it in an area selecting a separate bus at 16 bits,
input and output data (D
8
- D15).
External data bus
switch input
BYTE
I
Be terminals to switch an external data bus. In the case of "L" this terminal becomes
16 bits, in the case of "H" this terminal becomes
8
bits.
Fix it to either. Be connected to
V
SS with the single chip mode.
C
NV
SS
C
NV
SS
0
Be terminals to change a processor mode. After reset, when IC start a working
with a single chip mode, connect it to
V
SS, when IC start a working with a
microprocessor mode, connect to
V
CC1.
Reset input
RESET
I
The microcomputer becomes the reset state when you input "L" into this terminal.
HLDA
O
During the period of the hold state, this terminal outputs "L".
RDY
I
The bus of the microcomputer becomes the weight state the input of this terminal
during a period of "L".
