phyCORE-ADuC812 QuickStart Instructions
78
© PHYTEC Meßtechnik GmbH 2002 L-462e_2
5.3
Linking and Locating
The Linker must combine several relocatable object modules
contained in object files and/or libraries to generate a single absolute
object.
In addition, the linker must locate several segments of code and data
to fixed address locations within the address space in regards to the
memory types of the phyCORE-ADuC812. XDATA segments always
must be located to Random Access Memory (e.g. RAM), CODE
segments should be located to non-volatile memory (e.g. Flash). The
8051 family supports a Harvard memory architecture that
distinguishes between non-volatile and randomly accessible memory
and has two physically different signals for separate fetching of data
and code.
The Keil tool chain distinguishes the following segment types:
•
CODE: code
•
XDATA:external data (max. 64 kByte)
•
DATA: direct addressable on-chip data (max. 128 Byte)
•
IDATA: indirect addressable on-chip data (max. 256 Byte)
•
BIT:
bit-addressable on-chip data (max. 128-bits)
The segment types DATA, IDATA and BIT always reside in the
on-chip RAM of the controller.
The segment type XDATA will usually reside in external memory
devices. The segment type CODE will usually reside in external
memory devices or the on-chip Flash memory.
To ensure proper execution of your application, it is required that all
XDATA segments are located to the external RAM of the
phyCORE-ADuC812 and that all CODE segments are located to the
external Flash memory and on-chip Flash memory of the
phyCORE-ADuC812.
