Phytec 1488.2, Hardware Manual

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PCM-065/phyCORE-i.MX8X System on Module L-864e.A1
© PHYTEC America LLC, 2021 54
10 Camera Interfaces
The following subsections detail each of the camera interfaces supported on the phyCORE-i.MX8X.
10.1 MIPI CSI
The phyCORE-i.MX8X SOM provides a MIPI CSI-2 camera port with up to four data lanes and one clock lane
with programmable lane positions. The locations of the MIPI camera signals at the phyCORE-Connector are
listed in the table below.
Table 43. MIPI CSI Connections at the phyCORE-Connector
X1 Pin # Signal Type Level Processor Ball Description
D32 X_MIPI_CSI0_MCLK_OUT O 1.8V AN25 MIPI CSI0 Clock Out
D33 X_MIPI_CSI0_GPIO0_00 I/O 1.8V AR25 MIPI CSI0 GPIO0 0
D34 X_MIPI_CSI0_GPIO0_01 I/O 1.8V AP24 MIPI CSI0 GPIO0 1
D36 X_MIPI_CSI0_I2C0_SCL OD-O 1.8V AP26 MIPI CSI0 I2C0 Clock
D37 X_MIPI_CSI0_I2C0_SDA OD-I/O 1.8V AM24 MIPI CSI0 I2C0 Data
D46 X_MIPI_CSI0_DATA0_P I Differential AP22 MIPI CSI0 Data 0 Positive
D47 X_MIPI_CSI0_DATA0_N I Differential AM22 MIPI CSI0 Data 0 Negative
D41 X_MIPI_CSI0_DATA1_P I Differential AP20 MIPI CSI0 Data 1 Positive
D42 X_MIPI_CSI0_DATA1_N I Differential AM20 MIPI CSI0 Data 1 Negative
D48 X_MIPI_CSI0_DATA2_P I Differential AR23 MIPI CSI0 Data 2 Positive
D49 X_MIPI_CSI0_DATA2_N I Differential AN23 MIPI CSI0 Data 2 Negative
D38 X_MIPI_CSI0_DATA3_P I Differential AR19 MIPI CSI0 Data 3 Positive
D39 X_MIPI_CSI0_DATA3_N I Differential AN19 MIPI CSI0 Data 3 Negative
D43 X_MIPI_CSI0_CLK_P I Differential AR21 MIPI CSI0 Clock Positive
D44 X_MIPI_CSI0_CLK_N I Differential AN21 MIPI CSI0 Clock Negative
10.2 Parallel Camera Input Port
In addition to the MIPI camera interface, the phyCORE-i.MX8X SOM also provides a parallel camera interface
with the following support options:
•
8-bit/
10-bit BT.656
•
8-bit/24-bit data port for RGB, YCbCr, and YUV data input
•
8-bit/
12-bit/10-bit/16-bit data port for Bayer data input
Table 44. Parallel Camera Connections at the phyCORE-Connector
X1 Pin # Signal Name Type Level Processor Ball Description
D14 X_CSI_DO0 I 1.8V AK28 CSI Data out 0
D15 X_CSI_DO1 I 1.8V AL29 CSI Data out 1
D16 X_CSI_DO2 I 1.8V AP30 CSI Data out 2
D17 X_CSI_DO3 I 1.8V AJ27 CSI Data out 3
D19 X_CSI_DO4 I 1.8V AN29 CSI Data out 4
D20 X_CSI_DO5 I 1.8V AM30 CSI Data out 5
D21 X_CSI_DO6 I 1.8V AJ25 CSI Data out 6
D22 X_CSI_DO7 I 1.8V AM28 CSI Data out 7
D24 X_CSI_HSYNC I 1.8V AR29 CSI Horizontal Sync
D25 X_CSI_VSYNC I 1.8V AL27 CSI Vertical Sync
D26 X_CSI_EN I 1.8V AP28 CSI Enable
D27 X_CSI_RESET I 1.8V AR27 CSI Reset
D29 X_CSI_MCLK O 1.8V AM26 CSI Master Clock
D30 X_CSI_PCLK I 1.8V AK26 CSI Pixel Clock