PCM-065/phyCORE-i.MX8X System on Module
L-864e.A1
© PHYTEC America LLC, 2021
42
6
Serial Interfaces
The following subsections detail each of the serial interfaces supported on the phyCORE-i.MX8X.
6.1
CAN
The phyCORE-i.MX8X SOM provides three Flexible Controller Area Network (FlexCAN) ports. Both interfaces
support CAN and CAN FD (flexible data-rate) specifications, conforming with CAN protocol version 2.0 part B.
Table 19. FlexCAN Connections at the phyCORE-Connector
X1 Pin #
SOM Signal
Type
Level
Processor Ball
Description
A42
X_FLEXCAN0_RX
I
3.3V
T22
FlexCAN0 Receive Data
A41
X_FLEXCAN0_TX
O
3.3V
U25
FlexCAN0 Transmit Data
A43
X_FLEXCAN1_RX
I
3.3V
T24
FlexCAN1 Receive Data
A44
X_FLEXCAN1_TX
O
3.3V
U29
FlexCAN1 Transmit Data
A46
X_FLEXCAN2_TX
I
3.3V
U27
FlexCAN2 Transmit Data
A47
X_FLEXCAN2_RX
O
3.3V
T28
FlexCAN2 Receive Data
6.2
Ethernet
The phyCORE-i.MX8X SOM provides two external 10/100/1000 Mbps Ethernet ports. A DP83867IRRGZ
Ethernet PHY is populated on-board to translate the ENET0_RGMII signals to the differential Ethernet data pairs
that are accessible at the phyCORE-Connector. The DP83867 is a robust, low power transceiver that supports
10-BASE-Te, 100BASE-TX, and 1000BASE-T protocols to interface directly to twisted pair media through an
external transformer.
CAUTION:
Only ENET0 is translated with a DP83867. The ENET1 signals are not.
It is important to note that the i.MX8X is not rated for RGMII operation at 3.3V, which means RGMII signals
must be configured at 1.8V. When designing your own carrier board, ensure your Ethernet PHY is run at 1.8V
when connecting to ENET1.
In addition to the Ethernet data pairs, the on-board PHY also provides two LED control outputs and two GPIO
signals. Each of these signals can be configured for general multi-function uses depending on the application.
The GPIO and LED I/O also serve as bootstrap pins for PHY configuration. Be careful to avoid pulling or driving
these signals during power up and reset. Refer to the DP83867IRRGZ datasheet for details on these
configuration and strapping options.
Table 20. Ethernet Connections at the phyCORE-Connector
X1 Pin # SOM Signal
Type
Level
Processor Ball
Description
A62
X_ETH0_LED0/MAC_RXD3
O
3.3V
-
LED Link Signal
A63
X_ETH0_LED1/MAC_RXD2
O
3.3V
-
LED Activity Signal
A64
X_ETH_GPIO0
I/O
3.3V
-
SOM Ethernet PHY
GPIO 0
A65
X_ETH_GPIO1
I/O
3.3V
-
SOM Ethernet PHY
GPIO 1
B68
X_ETH0_A-/TX0-/MAC_TXD2
ETH_I/O
Differential
-
Ethernet Data A
Negative
B69
X/TX0+/MAC_TXD3
ETH_I/O
Differential
-
Ethernet Data A
Positive
