PCM-065/phyCORE-i.MX8X System on Module
L-864e.A1
© PHYTEC America LLC, 2021
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8
Debug Interfaces
The following subsections detail each of the debug interfaces supported on the phyCORE-i.MX8X.
8.1
JTAG
The phyCORE-i.MX8X SOM is equipped with a JTAG interface for downloading program code into the internal
RAM or for debugging programs currently executing. The JTAG interface is accessible via the phyCORE-
Connector and provides five standard IEEE1149.1/IEEE1149.6 JTAG signals. Please reference
for further information regarding the JTAG interface.
Table 39. JTAG Connections at the phyCORE-Connector
X1 Pin #
SOM Signal
Type
Level
Processor Ball
Description
D51
X_JTAG_TCK
I
1.8V
AE31
JTAG Test Clock
D52
X_JTAG_TDO
O
1.8V
AF32
JTAG Test Data Output
D53
X_JTAG_TDI
I
1.8V
AH34
JTAG Test Data Input
D54
X_JTAG_TMS
I
1.8V
AG35
JTAG Test Mode Select
D55
X_JTAG_TRST_B
I
1.8V
AB28
JTAG Reset
8.2
UART0
The phyCORE-i.MX8X SOM can also be communicated with using UART0 for downloading program code into
the internal RAM or for debugging programs currently executing. The UART interface is accessible via the
phyCORE-Connector.
Table 40. UART Connections at the phyCORE-Connector
X1 Pin #
SOM Signal
Type
Level
Processor Ball
Description
A48
X_UART0_TX
O
1.8V
U23
UART0 Transmit Data
A49
X_UART0_RX
I
1.8V
V28
UART0 Receive Data
