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Photon Focus MV-D752-28 User Manual Download Page 37

 

MV-D752-28  User’s Manual 

 

 

 

 

 
 

REV: 1.0 

      Page 37/61 

Table 24:  Mode register 0 (Register address REGADDR = 6D = 06H) 

 
MODE0_REG 
bit Name 

Description 

Default 

0 R/W_LUT 

= 

1 

Î

 Enable Read/Write RAM-LUT 

0 

1 USER_LUT 

= 

0 

Î

 USER-LUT0, =1 

Î

 USER-LUT1 

0 

2 POWER_SAVE = 

1 

Î

 power save mode ADC module 

0 

3 Not 

used 

- 

0 

4 Not 

used 

- 

0 

5 Not 

used 

- 

0 

6 Not 

used 

- 

0 

7 Not 

used 

- 

0 

 
 

11.2

 

Instructions for control of the ADC-Module 

 
Table 25 displays the defined commands. 

 

Table 25:  ADC-Module commands 

 

C Description 

3 

Execute EEPROM, access to the EEPROM starts according selected operation 

4 

Reload LUT, LUT-Data is copied from the EEPROM into the RAM-LUT 

 

Abbreviation: 
 
C: Command

 

 

Summary of Contents for MV-D752-28

Page 1: ...MV D752 28 CMOS area scan camera Camera User s Manual REV 1 0...

Page 2: ...ic CMOS sensors LinLogTM Technology was recognized with the Stuttgart Vision 2000 prize for innovation and more recently the Photonics Award of Excellence With these technologies blooming and smear be...

Page 3: ...e 9 10 2 7 Registers 18 20 for LinLog2 9 10 2 8 Registers 21 23 Frame time 9 10 2 9 Registers 24 31 ROI 9 10 2 10 Register 32 Line pause 9 10 2 11 Calculation of Frame time 9 10 2 12 Register 33 Line...

Page 4: ...9 23 Revisions and State of Product development 9 23 1 Revisions 9 23 2 State of Product development 9 24 Service information 9 24 1 Contact for product enquiries and quotations 9 24 2 Product informa...

Page 5: ...nfiguration needs no external control signals to acquire images The integration time and the read out window ROI are pre programmed in the camera via the configuration interface and can be changed by...

Page 6: ...8 bit Dynamic range in LinLogTM Mode 120 dB Analog amplification 1 or 4 Spectral range 400 nm 900 nm see Fig 1 Optical Fill factor 35 Data interface LVDS and CameraLink Data resolution 10 bit 8 bit or...

Page 7: ...MV D752 28 User s Manual REV 1 0 Page 7 61 2 Mechanical Dimensions The Front plate is compatible with the Microbench System of LINOS AG www linos de MB2002 Interface Camera Link 46 Interface L VDS...

Page 8: ...ELD Shield 2 O N_XD0 Negative LVDS Output CameraLink DataD0 3 O N_XD1 Negative LVDS Output CameraLink DataD1 4 O N_XD2 Negative LVDS Output CameraLink DataD2 5 O N_XCLK Negative LVDS Output CameraLink...

Page 9: ...ig 2 Connector socket Nr 09 0408 90 03 for the voltage supply Table 5 Data bit assignments for the 8 bit configuration Data bit CameraLink Port and bit LSB A0 LSB 1 A1 LSB 2 A2 LSB 3 A3 LSB 4 A4 LSB 5...

Page 10: ...e pin assignments for the LVDS interface of the Photonfocus camera series The interface definition contains the following 16 data signals 8 handshake signals for camera control by the frame grabber an...

Page 11: ...GND Ground 30 PW GND Ground 31 O NDATA1 Negative LVDS Output Data bit 1 32 O NDATA3 Negative LVDS Output Data bit 3 33 O NDATA5 Negative LVDS Output Data bit 5 34 O NDATA7 Negative LVDS Output Data b...

Page 12: ...ATA13 PDATA15 NDATA15 GROUND GROUND VDD VDD RX_RS232 TX_RS232 GROUND GROUND VDD VDD VDD2 VDD2 12 11 10 9 8 7 57 56 55 40 54 39 53 38 52 37 51 36 50 35 49 34 48 33 47 32 46 31 6 5 4 3 2 1 15 14 13 59 5...

Page 13: ...ut can be interrupted by a new trigger In this mode the user should ensure that the trigger rate and the frame rate correspond Fig 4 illustrates the function of the parameter constant image data rate...

Page 14: ...f the image information begins afresh The data are output on the rising edge of the pixel clock The signals FRAME_VALID FVAL and LINE_VALID LVAL mask valid image information The signal SHUTTER indicat...

Page 15: ...at of the frame grabber by means of the flag POLARITY_SYNC_EXPOSURE bit 3 mode register 3 The data are output on the rising edge of the pixel clock The signals FRAME_VALID FVAL and LINE_VALID LVAL mas...

Page 16: ...EXSYNC signal can be matched to that of the frame grabber by means of the flag POLARITY_SYNC_EXPOSURE bit 3 mode register 3 The image is read out after the exposure time has elapsed After readout the...

Page 17: ...grabber by means of the flag POLARITY_SYNC_EXPOSURE bit 3 mode register 3 The image is read out after the exposure time has elapsed After readout the sensor returns to the reset state and the camera...

Page 18: ...Falling Edge of signal Polarity TRIGGER START EXPOSURE START EXPOSURE STOP EXSYNC Mode internal exposure time via Register 1 FE_EXSYNC FE_EXSYNC EXPOSURE_END 1 RE_EXSYNC RE_EXSYNC EXPOSURE_END EXSYNC...

Page 19: ...ponse can be smoothly adjusted and is continuously differentiable This setting is achieved via DAC channel 4 in the voltage range 0 4V see Appendix E For many applications the logarithmic compression...

Page 20: ...onstant frame time the frame time should be set to a value that allows the sensor a reset time of at least 10 s Fig 10 Sensor response in Skim mode compared with linear response On the other hand it i...

Page 21: ...I the restriction described above can be removed by deactivating the pre load of line addresses This is achieved by deactivating bit 5 of mode register 3 address 0DH i e set EN_PRELOAD 0 and also sett...

Page 22: ...0 581 751 581 X0_ROI Y0_ROI X1_ROI Y0_ROI X1_ROI Y1_ROI X0_ROI Y1_ROI Fig 12 A single ROI bounded by X0_ROI Y0_ROI and X1_ROI Y1_ROI 64 Pixels valid ROI Line pause 8 EN_PRELOAD 1 valid ROI Line pause...

Page 23: ...rances of the centering of the optical axis on the sensor can be corrected For ideal centering of the optical axis of the camera on the sensor the following values of X_OFF and Y_OFF are used X_OFF 10...

Page 24: ...ode 8 bit resolution and linear response An example of initial sensor control values is summarized in Table 27 Since every camera is individually set up before delivery parameters will vary from those...

Page 25: ...djust camera modes 15 F R W LSB Exposure Time 16 10 R W MSB 1 Exposure Time 17 11 R W MSB Exposure Time 18 12 R W LSB LinLog Time 19 13 R W MSB 1 LinLog Time 20 14 R W MSB LinLog Time 21 15 R W LSB Fr...

Page 26: ...sed 46 2E Not used 47 2F R W Choice of a RAM bank for read write access 48 30 R W Byte0 of a 16x8 RAM Bank 49 31 R W Byte1 of a 16x8 RAM Bank 50 32 R W Byte2 of a 16x8 RAM Bank 51 33 R W Byte3 of a 16...

Page 27: ...rror bits in status register 4 can be reset by writing a logical 1 to the corresponding bit The definitions of the individual bits of these registers are summarized in Table 11 and Table 12 Bit 0 and...

Page 28: ...a in operation 1 1 ENABLE1 Invert Pixel Clock 1 phase shift of 180 degrees 0 2 ENABLE2 0 3 ENABLE3 These bits are responsible for resolution access to the LUT s and the LFSR interface test 0 4 EN_TOGG...

Page 29: ...d not be set in this mode Bit 7 register 6 activates the LinLog mode It is used by the internal state machines to generate the LinLog characteristic Consequently this value toggles between 0 and 1 whe...

Page 30: ...e Description Voltage range V 0 VB1 External force VB1 pixel bias 0 6 0 8 1 VB2 External force VB2 column bias 2 0 2 4 2 VB3 External force VB3 output bias 0 7 0 9 3 VSH Shutter voltage 0 0 4 0 4 VLOG...

Page 31: ...of a line 0 7 EN_HOLD_READOUT 1 enable HOLD function in development 0 Table 19 Mode register 4 register address REGADDR 14D 0EH Register address 14 MODE4_REG bit Name Description Default 0 SLAVE_ACTI...

Page 32: ...n increments of the pixel clock 35 ns in case of the internal camera clock as both of the above time values The frame pause is used to keep the frame rate constant independent of the exposure time NOT...

Page 33: ...u must match the frequency used A calculator for calculating frame rate is available at www photonfocus com 10 2 12 Register 33 Line jump and pixel jump This register contains the value for the interl...

Page 34: ...rors can be identified in the complete image processing system LOG Mode Pure logarithmic mode the pixels function as simple photo diodes and are continuously exposed to the light source Because of the...

Page 35: ...ble After accessing the ADC module the camera must be reset to slave mode where the external clock is used Table 22 Register 0 to 63 of the ADC module REG DEC REG HEX W or C Function during WRITE R Fu...

Page 36: ...cause otherwise incorrect information will get into the internal camera register The PROM_BUSY state indicates an uncompleted writing cycle active memory load during write access to the EEPROM EEPROM...

Page 37: ...LUT1 0 2 POWER_SAVE 1 power save mode ADC module 0 3 Not used 0 4 Not used 0 5 Not used 0 6 Not used 0 7 Not used 0 11 2 Instructions for control of the ADC Module Table 25 displays the defined comma...

Page 38: ...ks It is imperative that no pressure be applied to the surface of the sensor or to the Globe Top surrounding the optically active surface during the cleaning process The use of pointed or sharp object...

Page 39: ...ly the byte 00H is the factory setting in the EEPROM The factory settings contain all parameters which are needed for the operation of the camera after power up or reset Table 27 shows the EEPROM addr...

Page 40: ...DAC0 Channel Register 6 W 11 8 10 Chan6_Ctl_MSB MSB DAC0 Channel Register 6 W 12 9 5A Chan7_Ctl_LSB LSB DAC0 Channel Register 7 W 13 8 10 Chan7_Ctl_MSB MSB DAC0 Channel Register 7 W 14 9 5E Chan0_Mai...

Page 41: ...ter 3 R W 36 D 20 MODE4 7 0 Mode register 4 R W 37 E 00 EXPOSURE_TIME 7 0 LSB Exposure time R W 38 F E0 EXPOSURE_TIME 15 8 MSB 1 Exposure time R W 39 10 93 EXPOSURE_TIME 23 16 MSB Exposure time R W 3A...

Page 42: ...BYTE5 7 0 No LinLog MSB LL2 R W 62 35 30 BANK0_BYTE6 7 0 Log Parameter LSB R W 63 36 F4 BANK0_BYTE7 7 0 Log Parameter MSB R W 64 37 31 BANK0_BYTE8 7 0 LinLog Parameter LSB LL1 R W 65 38 BC BANK0_BYTE9...

Page 43: ...C0 Channel 2 Main register Base 0A LSB DAC0 Channel 2 Sub register Base 0B MSB DAC0 Channel 2 Sub register Base 0C LSB DAC0 Channel 3 Main register Base 0D MSB DAC0 Channel 3 Main register Base 0E LSB...

Page 44: ...ues higher than 511 will be displayed as a gray values of 511 Clamping LUT1 contains a LUT with a digital amplification of 4 and a gray scale clamping of 255 Fig 13 shows the clamping of the initial v...

Page 45: ...to the 8 bit RS232 limitation it is not possible to distinguish between data and address transfers The protocol in Table 31 is implemented to allow access to the 64 internal camera registers Table 31...

Page 46: ...rite Low Data Nibble 5 4 TX 0000 0110 06 Successful receipt camera transmits ACK 06H 5 RX 1100 0101 C5 Write High Data Nibble 5 6 TX 0000 0110 06 Successful receipt camera transmits ACK 06H 7 RX 0100...

Page 47: ...g is shown in Table 34 In order to be able to write to the EEPROM the write protection must be disabled The PROM_BUSY and the AUTOLOAD flag in the EEPROM register address 4 bit 1 or bit 0 must also be...

Page 48: ...n register address 02H 4 Read status register address 04H wait for state not PROM_BUSY or AUTOLOAD 5 Write in register address 03H command SEND_PROM 6 Read status register address 04H wait for state n...

Page 49: ...Table 37 Table 37 Individual control parameters BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 System control X 0 0 X X X X X 0 BIN PD SSTBY SCLR 0 X X Channel control X 1 0 A2 A1 A0 MX1 MX0 X X X STBY CL...

Page 50: ...5A10 Active output external reference Vref 1 25V Channel register 7 5E10 Active output external reference Vref 1 25V The output voltage is determined by the following equation 4096 128 1024 512 875 1...

Page 51: ...0100100 42 3C8 0001001111 74 0FF 1111111100 106 2BB 1101110101 11 126 0110010010 43 391 1000100111 75 1FF 1111111110 107 177 1110111010 12 24D 1011001001 44 323 1100010011 76 3FF 1111111111 108 2EF 11...

Page 52: ...0100 142 17F 1111111010 174 291 1000100101 206 233 1100110001 238 14F 1111001010 143 2FF 1111111101 175 123 1100010010 207 067 1110011000 239 29F 1111100101 144 1FE 0111111110 176 246 0110001001 208 0...

Page 53: ...Code signal REG STD_LOGIC_VECTOR 9 downto 0 signal DATAIN STD_LOGIC SR10R process ICLK 10 bit LFSR begin if ICLK event and ICLK 1 then if RESET 1 then reset shift register is loaded with 1 REG 000000...

Page 54: ...MV D752 28 User s Manual REV 1 0 Page 54 61 19 Appendix G CE Test Compliance...

Page 55: ...N 0 9651934 3 8 20 2 Files on the web server www photonfocus com AN001 Application note LinLog2 AN001 Photonfocus AG CLO2000 Specifications of the Camera Link Interface Standard for Digital Cameras an...

Page 56: ...ss REGADDR 12D 0CH 9 Table 18 Mode register 3 Register address REGADDR 13D 0DH 9 Table 19 Mode register 4 register address REGADDR 14D 0EH 9 Table 20 Camera control commands 9 Table 21 Overview of the...

Page 57: ...Diagram Free Running Mode 9 Fig 6 Timing Diagram Trigger Mode 9 Fig 7 Timing Diagram Trigger Mode with external edge triggered exposure control 9 Fig 8 Timing Diagram Sync Exposure Mode 9 Fig 9 Respon...

Page 58: ...MV D752 28 User s Manual REV 1 0 Page 58 61 23 Revisions and State of Product development 23 1 Revisions Table 40 Document revisions REV Changes Date 1 0 First edition 30 07 03...

Page 59: ...rmware revision camera serial number software revision and revision of the user manual This table indicates firmware documents and software revisions Table 41 Correlation between firmware software and...

Page 60: ...amera from its packing and ensure that it is complete and undamaged If any damage has occurred during transport please immediately contact the transport company and your distributor The camera is deli...

Page 61: ...of damage If the equipment is defective return it in the original packing and with a copy of the receipt to the following address Photonfocus AG Bahnhofplatz 10 CH 8853 Lachen Important Include a writ...

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