MV-D752-28 User’s Manual
REV: 1.0
Page 32/61
Bit 6 activates the half-line reset. When used with Skim mode, the sensor can be put into
an extended rest phase resulting, with certain settings, in the production of image
artifacts. Photonfocus recommends that this bit be deactivated.
Bit 7 activates the HOLD_READOUT mode, which allows transmission to be interrupted
when the CONTROL signal is active. The ‘hold’ occurs after the end of a line.
10.2.6
Registers 15-17: Exposure time
The exposure time (parameter Exposuretime) is implemented in a 24 bit register. This
register consist of three 8 bit registers register 15-17. This value is also set in increments
of the pixel clock (35 ns in case of the internal camera clock). The exposure time can be
varied during read out of the sensor, because actual value is stored in a shadow register.
10.2.7
Registers 18-20: for LinLog2
The LinLog2 time constant is also implemented as a 24 bit register (registers 18-20), just
as the exposure time. The LinLog2 time constant must always be smaller than the
exposure time.
10.2.8
Registers 21-23: Frame time
The frame pause is set by register 21-23. This value is also set in increments of the pixel
clock (35 ns in case of the internal camera clock) as both of the above time values. The
frame pause is used to keep the frame rate constant, independent of the exposure time.
NOTICE:
the frame rate sets the maximum exposure time. Invalid values must be
prevented via software.
10.2.9
Registers 24-31: ROI
The registers 24-31 are used to define the region of interest of the sensor (see Fig.12).
The coordinates of the corners of the ROI can be written at every time into the shadow
registers. After read out of a frame the values of the shadow registers are mirrored into
the working registers. Invalid values must be prevented via software. Values x
0
> x
1
or
y
0
> y
1
are ignored by the camera. In this cases the coordinates of the corners of the ROI
are x
0
= 0 and x
1
= 751 or y
0
= 0 and y
1
= 581.
When changing the ROI, note that
some frame grabbers expect defined line and row settings and these values
must be updated in the corresponding files.
10.2.10
Register 32: Line pause
This register holds the line pause value, in units of the pixel clock (t
u
= 35ns). The range
of values is 8 .. 255. If the pre-load of line addresses is deactivated, then the minimum
line pause of 8 cannot be reached!
When changing the line pause, note that some
frame grabbers expect defined line pause settings and these values must be
updated in the corresponding files.