MV-D752-28 User’s Manual
REV: 1.0
Page 10/61
3.2
LVDS Interface
To implement the LVDS (RS644) interface, the Molex 60 pole Low Force Helix (LFH60)
plug system was used. This very compact plug system possess the property that the
insertion force at the start of the insertion is very low and increases steadily as the plug
is introduced. Due to the use of two contact points for each plug contact, the safety of
the connection is substantially higher than that of other conventional systems. The
Photonfocus LVDS Interface combines data and control signals as well as current supply
on one socket. This has the advantage for the user that only one cable is needed
between camera and frame grabber.
The contact pin sequence of the LFH60 system
was altered from that used by the manufacturer (Molex).
Only the position of
contact 1 is identical in the two systems. In contrast to the Molex system, in which the
contacts are numbered in a meandering fashion, Photonfocus begins the count a new at
the top of each column. The Photonfocus definitions are made clear in Table 7 and Fig. 3.
Fig. 3 illustrate the pin assignments for the LVDS interface of the Photonfocus camera
series. The interface definition contains the following: 16 data signals, 8 handshake
signals for camera control by the frame grabber, an RS232 interface for camera set-up,
as well as voltage supply. The 16 data signals can be used in different ways, depending
on the camera type. The MV-D752-28LV-10 uses only the lower 10 bits (DATA0 ...
DATA9). In the 8 bit camera mode, the top 2 bits (DATA 9 und DATA 8) are set LOW
internally and thus deactivated. The 8 handshake lines are divided between 4 input
signals and 4 output signals. Input signals comprise the external trigger EXSYNC, the
external exposure control EXPOSURE, the external clock signal for the slave mode
(master clock) MCLK and an external camera control signal CONTROL. The camera output
signals FRAME_VALID, LINE_VALID and PIXEL_CLK are modeled on the AIA interface
[AIA]. FRAME_VALID high indicates an active image transfer. LINE_VALID high denotes
an active line. The digital data for the individual pixels are output on the rising edge of
PIXEL_CLK. In addition to these signals, the signal SHUTTER is defined to be high during
the integration phase of the sensor. This signal permits the synchronization of external
light sources e.g. a flash light (see section Timing Diagram).