Philips LX9000R/22, Service Manual

Page: 177 / 251

Circuit-, IC descriptions and list of abbreviations EN 177 LX9000R 9.
Pin # Name Description
Control Signals (contd.)
52 NOMEM No Memory Mode control input. This pin controls the operation of the FLI2200 as follows:
When this pin is set low the device is used with external field memories and operates in the full
set of deinterlacing modes, i.e., motion adaptive video deinterlacing and full frame film source
deinterlacing using 3:2 pulldown detection (2:2 pulldown for 625/50 sources). When this pin is
set high the FLI2200 is forced into the intra-field only deinterlacing mode, which requires no
external memories, allowing the FLI2200 to be used in low-cost applications where the ultimate
video quality is not a requirement.
To ensure proper startup of the SDRAMs this pin should be
set high during the power-up sequence. This can be overridden by the NMOvr bit, bit 1 in
register 05
H
, allowing this function to be set or changed via the I
2
C bus. Please refer to the
description of register 05
H
for details.
Input Signals
27-18 G/YIN
9-0
10-bit green or luminance signal input bus. The mode is set by the IFORMAT
2-0
pins. This can
be overridden by the IFmtOvr bit, bit 3 in register 00
H
, allowing this function to be set or
changed via the I
2
C bus. Please refer to the description of register 00
H
for details. This
signal is sampled on the rising edge of PIXCLK.
15-6 B/CbIN
9-0
10-bit blue or Cb chroma signal input bus. The mode is set by the IFORMAT
2-0
pins.
This can be overridden by the IFmtOvr bit, bit 3 in register 00
H
, allowing this function to be
set or changed via the I
2
C bus. Please refer to the description of register 00
H
for details. Bits 6,
4 and 3 in register 08
H
specify the busses used in the multiplexed modes. In all cases the
signals are sampled on the rising edges of PIXCLK. In the Y Cb Cr and Y Pb Pr modes the Cb or
Pb signal is sampled on alternate rising edges of PIXCLK in 4:2:2 mode. The frequency of
PIXCLK will be 27 MHz in the multiplexed Y/Cb/Cr mode and 13.5 MHz in all other modes.
These pins should be tied low when not used.
39-35 R/CrIN
9-0
10-bit red or Cr chroma signal input bus. The mode is set by the IFORMAT
2-0
pins.
32-28 This can be overridden by the IFmtOvr bit, bit 3 in register 00
H
, allowing this function to be
set or changed via the I
2
C bus. Please refer to the description of register 00
H
for details. Bits 6,
4 and 3 in register 08
H
specify the busses used in the multiplexed modes. In all cases the
signals are sampled on the rising edges of PIXCLK. In the Y Cb Cr mode the Cr signal is
sampled on alternate rising edges of PIXCLK in 4:2:2 mode. The frequency of PIXCLK will
be 27 MHz in the multiplexed Y/Cb/Cr mode and 13.5 MHz in all other modes. These pins
should be tied low when not used.
3 HSYNCREFI Horizontal sync or reference. The horizontal sync or reference of the input signal should be
connected to this pin. The function is programmed with bit 4 in register 00
H
. The polarity
and position of the sync or reference pulse relative to the start of active video are both
programmable within a small range. When the FLI2200 is used in the ITU-R BT 601/D1 input
mode with embedded syncs (IFormat = 110) this input is not used and should be tied low; in
this case all sync information will be derived from the signal.
4 VSYNCREFI Vertical sync or reference. The vertical sync or reference of the input signal should be
connected to this pin. The function is programmed with bit 4 in register 00
H
. The polarity
and position of the sync or reference pulse relative to the start of active video are both
programmable within a small range. When the FLI2200 is used in the ITU-R BT 601/D1 input
mode with embedded syncs (IFormat = 110) this input is not used and should be tied low; in
this case all sync information will be derived from the signal.
5 FLDIN Field identifier input. The field identifier output of the source signal should be connected to
this pin. A low setting signifies an even field and a high level signifies an odd field. When
bit 4 in register 00
H
is set low, the input timing is based on HREF and VREF and this signal
is required. When this bit is set high the input timing is based on HSYNC and VSYNC and this
signal is generated internally and is not required. When bit 5 in register 06 is set high this
signal is also used as the frame boundary identifier for 30 Hz film sources.