Philips LX9000R/22, Service Manual

Page: 147 / 251

Circuit-, IC descriptions and list of abbreviations EN 147 LX9000R 9.
9.6.3 Functional Description
The DVIO module consists of the following blocks (see
blockdiagram):
1.
IEEE1394 Interface
•
uPD72852 (7400) (Phy)
• uPD72893 (7431) (Link part)
2. Micro-controller
•
uPD78F0988 (7802)
• Voltage regulator LM2931 for generation of 10V
programming voltage (7801)
3. Reset-circuitry
•
Power-on reset
• Reset pulse-shortener
4. DV-Decoder
•
uPD72893 (7431) (Codec part)
• 16MBit SDRAM (7430)
• optional Flah-Memory M29W800AT for Firmware-
Update of uPD72893 (7432)
5. Clocking & Audio PLL
•
Clock oscillator FXO-31FT (7601)
• Audio-PLL: Voltage controlled oscillator BA7082F
(7604), clock generator BU2288FV (7605), and clock
divider 74LV74 (7606-A)
6. Audio Format adaption (MSB justified -> I2S), option
•
74LV74 (7507-A, -B)
7. Audio & Video output
•
Audio DAC UDA1334ATS(7602)
• Clock delay(7500)
• Tristate buffer(7505)
IEEE1394 Interface
The 1394 interface consists of a uPD72852 physical layer and
a uPD72893 link layer IC (uPD72893 integrated also DV-
Decoder).
It has the following features:
•
S400 operation (400 megabit per second)
• Two i.Link ports (4 pin), only one used
• AV link port
Micro-Controller
The uPD78F0988 processor has following extra features:
•
60 kilobyte of flash memory as program memory
• 2 kilobyte of internal data memory
• watchdog timer
• On board ISP(In-System-Programming) functionality
ISP
By use of In-System-Programming, it is possible to update the
software of the DVIO board that is in the uPD78F0988. ISP can
be made active by resetting the processor and keeping the
ISPN pin low during reset. During ISP, the ISPN signal on the
board has to be kept low. A programming voltage of 10V is
activeted by the uPD78F0988 itself at the Vpp pin before
programming procedure starts. When the ISP mode is active,
the new program can be sent to the microprocessor through
the serial port.
Reset-circuitry
The reset-circuitry consists of two parts.
First part (around transistor 7803) generates a reset pulse
when the board is powered up.
Second part (around transistors 7804 & 7805) acts as a reset-
pulse shortener, i.e. a short reset pulse (4ms) is generated
from the input signal RESETn which is much longer (usually
100ms). This is required to ensure correct operation of the
Micro-controller after booting-up when RESETn is again
deactivated
DV-Decoder
The uPD72893 decodes the stream into video data in 656
format and audio data in I2S format.
The microprocessor has the ability to read the status registers
of the uPD72893. By reading these registers, extra data from
the DV stream, that is not decoded into audio or video, can be
sent to the digital board using pin TXD of the serial interface.
This data includes time stamp and some more.
Clocking and Audio PLL
The FXO-31FT generates the free-running 27MHz system
clock. Video part of input DV-stream is in the uPD72893
adapted to the local 27MHz clock domain (skip, repeat frame).
Because audio clock (11.2896Mz [fs=44.1kHz] or 12.288MHz
[fs=32kHz, 48kHz]).
The uPD72893 integrates the phase comparator that drives the
VCO BA7082F to a nominal frequency of 27MHz which in turn
is converted by BU2288FV and 74LV74 to 11.2896MHz or
12.288Mhz, respectively.
The uPD72893 controls directly the frequency ratio of the
BU2288FV.
Audio Format adaptation (MSB justified -> I2S), option
Due to a bug in 1st version of uPD72893 digital audio output is
not correct in I2S mode when in 32kHz operation. As a
workaround uPD72893 is generally configured in MSB justified
mode and conversion to I2S mode is done externally via a
74LV74 device.
Can be disabled with later versions of uPD72893.
Audio & Video Output
The audio I2S data are sent to audio DAC UDA1334. Analog
audio left and right signals are connected to the analog board.
The tri-state buffer enables the digital video stream to the Video
Input Processor on the digital board when the DV source is
selected.
The clock delay synchronizes the AV clock with the AV data at
the output.
9.7 EPG Nafta Board
9.7.1 General
Two ASICs from Gemstar, GS501 (item 7100) and GS502
(item 7201), generate the EPG OSD. The host P controls both
ICs via the I2C bus (pins 45 and 48). A RAM memory (item
7102) and a Flash memory with the firmware (item 7101)
belong also to the periphery of these ASICs.
A PIC processor (item 7303) generates the POR_N reset for
this system. The POR_DC reset comes from the set, and is
active after AC power 'on'. A port expander from the host,
controls the EXT_RESET signal. This port expander (item
7200) is also used for switching the video paths on the EPG
board.
Either the board works in 'Loop Trough' mode, or (for EPG) the
output path is switched to the 'EPG RGB' video.