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Philips LPC2101, User Manual

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© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

User manual

Rev. 01 — 12 January 2006 

160

Philips Semiconductors

UM10161

Volume 1

Chapter 12: SPI

  

Note that a read or write of the SPI data register is required in order to clear the SPIF 
status bit. Therefore, if the optional read of the SPI data register does not take place, a 
write to this register is required in order to clear the SPIF status bit.

12.2.5 Slave 

operation

The following sequence describes how one should process a data transfer with the SPI 
block when it is set up to be a slave. This process assumes that any prior data transfer has 
already completed. It is required that the system clock driving the SPI logic be at least 8X 
faster than the SPI.

1. Set the SPI control register to the desired settings.

2. Write the data to transmitted to the SPI data register (optional). Note that this can only 

be done when a slave SPI transfer is not in progress.

3. Wait for the SPIF bit in the SPI status register to be set to 1. The SPIF bit will be set 

after the last sampling clock edge of the SPI data transfer.

4. Read the SPI status register.

5. Read the received data from the SPI data register (optional).

6. Go to step 2 if more data is required to transmit.

Note that a read or write of the SPI data register is required in order to clear the SPIF 
status bit. Therefore, at least one of the optional reads or writes of the SPI data register 
must take place, in order to clear the SPIF status bit.

12.2.6 Exception 

conditions

12.2.7 Read 

overrun

A read overrun occurs when the SPI block internal read buffer contains data that has not 
been read by the processor, and a new transfer has completed. The read buffer containing 
valid data is indicated by the SPIF bit in the status register being active. When a transfer 
completes, the SPI block needs to move the received data to the read buffer. If the SPIF 
bit is active (the read buffer is full), the new receive data will be lost, and the read overrun 
(ROVR) bit in the status register will be activated.

12.2.8 Write 

collision

As stated previously, there is no write buffer between the SPI block bus interface, and the 
internal shift register. As a result, data must not be written to the SPI data register when a 
SPI data transfer is currently in progress. The time frame where data cannot be written to 
the SPI data register is from when the transfer starts, until after the status register has 
been read when the SPIF status is active. If the SPI data register is written in this time 
frame, the write data will be lost, and the write collision (WCOL) bit in the status register 
will be activated.

Summary of Contents for LPC2101

Page 1: ...C2101 02 03 User Manual Rev 01 12 January 2006 User manual Document information Info Content Keywords LPC2101 LPC2102 LPC2103 ARM ARM7 embedded 32 bit microcontroller Abstract An initial LPC2101 02 03 user manual revision ...

Page 2: ...miconductors Preliminary UM Volume 1 Preliminary UM Contact information For additional information please visit http www semiconductors philips com For sales office addresses please send an email to sales addresses www semiconductors philips com Revision history Rev Date Description 01 20060112 Initial version ...

Page 3: ...p to 13 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems 1 2 Features 16 bit 32 bit ARM7TDMI S microcontroller in a tiny LQFP48 package 2 kB 4 kB 8 kB of on chip static RAM and 8 kB 16 kB 32 kB of on chip flash program memory 128 bit wide interface accelerator enables high speed 70 MHz operation In System I...

Page 4: ...n support the ARM7 Local Bus for interface to on chip memory controllers the AMBA Advanced High performance Bus AHB for interface to the interrupt controller and the ARM Peripheral Bus APB a compatible superset of ARM s AMBA Advanced Peripheral Bus for connection to on chip peripheral functions The LPC2101 02 03 configures the ARM7TDMI S processor in little endian byte order AHB peripherals are al...

Page 5: ...ictions or applications where code density is an issue The key idea behind THUMB is that of a super reduced instruction set Essentially the ARM7TDMI S processor has two instruction sets The standard 32 bit ARM instruction set A 16 bit THUMB instruction set The THUMB set s 16 bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM s perfor...

Page 6: ... being 0 addresses ending with 0 2 4 6 8 A C and E in hexadecimal notation and data accessed as words to originate from addresses with address lines 0 and 1 being 0 addresses ending with 0 4 8 and C in hexadecimal notation This rule applies to both off and on chip memory usage The SRAM controller incorporates a write back buffer in order to prevent CPU stalls during back to back writes The write b...

Page 7: ...kB 16 kB 32 kB FLASH ARM7TDMI S LPC2101 2102 2103 INTERNAL SRAM CONTROLLER 2 kB 4 kB 8 kB SRAM ARM7 local bus APB ARM peripheral bus SCL0 SCL1 1 SDA0 SDA1 1 3 CAP0 1 4 CAP1 1 3 CAP2 1 3 MAT0 1 4 MAT1 1 3 MAT2 1 4 MAT3 1 AD0 7 0 I2C BUS SERIAL INTERFACES 0 AND 1 CAPTURE COMPARE EXTERNAL COUNTER TIMER 0 TIMER 1 TIMER 2 TIMER 3 EINT2 to EINT0 1 EXTERNAL INTERRUPTS SCK0 SCK1 1 MOSI0 MOSI1 1 MISO0 MISO...

Page 8: ...01 12 January 2006 User manual Fig 2 System memory map 0 0 GB 1 0 GB 8 kB ON CHIP NON VOLATILE MEMORY 0x0000 2000 0x0000 1FFF 0x0000 0000 RESERVED ADDRESS SPACE 2 kB ON CHIP STATIC RAM LPC2101 4 kB ON CHIP STATIC RAM LPC2102 8 kB ON CHIP STATIC RAM LPC2103 RESERVED ADDRESS SPACE 0x4000 0800 0x4000 07FF 0x4000 1000 0x4000 0FFF 0x4000 2000 0x4000 1FFF 0x4000 0000 2 0 GB 0x8000 0000 BOOT BLOCK 0x7FFF...

Page 9: ...re divided up into 128 peripherals Each peripheral space is 16 kilobytes in size This allows simplifying the address decoding for each peripheral All peripheral register addresses are word aligned AHB section is 128 x 16 kB blocks totaling 2 MB APB section is 128 x 16 kB blocks totaling 2MB Fig 3 Peripheral memory map RESERVED RESERVED 0xF000 0000 0xEFFF FFFF APB PERIPHERALS 0xE020 0000 0xE01F FFF...

Page 10: ...accesses to occur at smaller boundaries An implication of this is that word and half word registers must be accessed all at once For example it is not possible to read or write the upper byte of a word register separately Fig 4 AHB peripheral map VECTORED INTERRUPT CONTROLLER AHB PERIPHERAL 0 0xFFFF F000 4G 4K 0xFFFF C000 0xFFFF 8000 AHB PERIPHERAL 125 AHB PERIPHERAL 124 AHB PERIPHERAL 3 AHB PERIP...

Page 11: ... portion of the Boot Block and SRAM spaces need to be re mapped in order to allow alternative uses of interrupts in the different operating modes described in Table 4 Re mapping of the interrupts is accomplished via the Memory Mapping Control feature Section 3 7 Memory mapping control on page 23 Table 2 APB peripheries and base addresses APB peripheral Base address Peripheral name 0 0xE000 0000 Wa...

Page 12: ...mplish the branch to the interrupt handlers There are three reasons this configuration was chosen 1 To give the FIQ handler in the Flash memory the advantage of not having to take a memory boundary caused by the remapping into account Table 3 ARM exception vector locations Address Exception 0x0000 0000 Reset 0x0000 0004 Undefined Instruction 0x0000 0008 Software Interrupt 0x0000 000C Prefetch Abor...

Page 13: ...a reserved or unassigned address region The regions are Areas of the memory map that are not implemented for a specific ARM derivative For the LPC2101 02 03 this is Address space between on chip Non Volatile Memory and on chip SRAM labelled Reserved Address Space in Figure 2 For 32 kB Flash device this is memory address range from 0x0000 8000 to 0x3FFF FFFF for 16 kB Flash device this is memory ad...

Page 14: ... exception is generated for any instruction fetch that maps to an AHB or APB peripheral address Within the address space of an existing APB peripheral a data abort exception is not generated in response to an access to an undefined address Address decoding within each peripheral is limited to that needed to distinguish defined registers within the peripheral itself For example an access to address...

Page 15: ...description X1 Input Crystal Oscillator Input Input to the oscillator and internal clock generator circuits X2 Output Crystal Oscillator Output Output from the oscillator amplifier EINT0 Input External Interrupt Input 0 An active LOW HIGH level or falling rising edge general purpose interrupt input This pin may be used to wake up the processor from Idle or Power down modes Pin P0 16 can be selecte...

Page 16: ...L on page 24 for details and frequency limitations The onboard oscillator in the LPC2101 02 03 can operate in one of two modes slave mode and oscillation mode Table 6 Summary of system control registers Name Description Access Reset value 1 Address External Interrupts EXTINT External Interrupt Flag Register R W 0 0xE01F C140 INTWAKE Interrupt Wake up Register R W 0 0xE01F C144 EXTMODE External Int...

Page 17: ... CL and RS Capacitance CP in Figure 6 drawing c represents the parallel package capacitance and should not be larger than 7 pF Parameters FC CL RS and CP are supplied by the crystal manufacturer Choosing an oscillation mode as an on board oscillator mode of operation limits FOSC clock selection to 1 MHz to 30 MHz Fig 6 Oscillator modes and models a slave mode of operation b oscillation mode of ope...

Page 18: ...ce from Power down mode 15 MHz 20 MHz 10 pF 220 Ω 18 pF 18 pF 20 pF 140 Ω 38 pF 38 pF 30 pF 80 Ω 58 pF 58 pF 20 MHz 25 MHz 10 pF 160 Ω 18 pF 18 pF 20 pF 90 Ω 38 pF 38 pF 30 pF 50 Ω 58 pF 58 pF 25 MHz 30 MHz 10 pF 130 Ω 18 pF 18 pF 20 pF 50 Ω 38 pF 38 pF 30 pF NA NA Fig 7 FOSC selection algorithm Table 7 Recommended values for CX1 X2 in oscillation mode crystal and external components parameters Fu...

Page 19: ...leared Otherwise the event that was just triggered by activity on the EINT pin will not be recognized in the future Important whenever a change of external interrupt operating mode i e active level edge is performed including the initialization of an external interrupt the corresponding bit in the EXTINT register must be cleared For details see Section 3 5 4 External Interrupt Mode register EXTMOD...

Page 20: ...o it except in level sensitive mode when the pin is in its active state e g if EINT0 is selected to be LOW level sensitive and a LOW level is present on the corresponding pin this bit can not be cleared this bit can be cleared only when the signal on the pin becomes HIGH 0 1 EINT1 In level sensitive mode this bit is set if the EINT1 function is selected for its pin and the pin is in its active sta...

Page 21: ...ge 66 and enabled in the VICIntEnable register see Section 5 4 4 on page 48 can cause interrupts from the External Interrupt function though of course pins selected for other functions may cause interrupts from those functions Note Software should only change a bit in this register when its interrupt is disabled in the VICIntEnable register and should write the corresponding 1 to the EXTINT regist...

Page 22: ... EXTMODE0 1 EXTPOLAR1 0 EINT1 is low active or falling edge sensitive depending on EXTMODE1 0 1 EINT1 is high active or rising edge sensitive depending on EXTMODE1 2 EXTPOLAR2 0 EINT2 is low active or falling edge sensitive depending on EXTMODE2 0 1 EINT2 is high active or rising edge sensitive depending on EXTMODE2 7 3 Reserved user software should not write ones to reserved bits The value read f...

Page 23: ...trol and Status flags register SCS address 0xE01F C1A0 bit description Bit Symbol Value Description Reset value 0 GPIO0M GPIO port 0 mode selection 0 0 GPIO port 0 is accessed via APB addresses in a fashion compatible with previous LCP2000 devices 1 High speed GPIO is enabled on GPIO port 0 accessed via addresses in the on chip memory range This mode includes the port masking feature described in ...

Page 24: ...cy range while the PLL is providing the desired output frequency The output divider may be set to divide by 2 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle A block diagram of the PLL is shown in Figure 9 PLL activation is controlled via the PLLCON register The PLL multiplier and divider values are controlled ...

Page 25: ...figuration Register Holding register for updating PLL configuration values Values written to this register do not take effect until a valid PLL feed sequence has taken place R W 0 0xE01F C084 PLLSTAT PLL Status Register Read back register for PLL control and configuration information If PLLCON or PLLCFG have been written to but a PLL feed sequence has not yet occurred they will not reflect the cur...

Page 26: ... of the multiplier and divider values Connecting the PLL causes the processor and all chip functions to run from the PLL output clock Changes to the PLLCON register do not take effect until a correct PLL feed sequence has been given see Section 3 8 7 PLL Feed register PLLFEED 0xE01F C08C and Section 3 8 3 PLL Configuration register PLLCFG 0xE01F C084 on page 27 Fig 9 PLL block diagram CD 2P CLOCK ...

Page 27: ...the time it is read as well as the PLL status PLLSTAT may disagree with values found in PLLCON and PLLCFG because changes to those registers do not take effect until a proper PLL feed has occurred see Section 3 8 7 PLL Feed register PLLFEED 0xE01F C08C Table 16 PLL Control register PLLCON address 0xE01F C080 bit description Bit Symbol Description Reset value 0 PLLE PLL Enable When one and after a ...

Page 28: ... software should not write ones to reserved bits The value read from a reserved bit is not defined NA 8 PLLE Read back for the PLL Enable bit When one the PLL is currently activated When zero the PLL is turned off This bit is automatically cleared when Power down mode is activated 0 9 PLLC Read back for the PLL Connect bit When PLLC and PLLE are both one the PLL is connected as the clock source fo...

Page 29: ...ait for lock and then connect the PLL can be called at the beginning of any interrupt service routine that might be called due to the wake up It is important not to attempt to restart the PLL by simply feeding it when execution resumes after a wake up from Power down mode This would enable and connect the PLL at the same time before PLL lock is established 3 8 9 PLL frequency calculation The PLL e...

Page 30: ...ces may be running from a lower clock than the processor see Section 3 11 APB divider on page 36 2 Choose an oscillator frequency FOSC CCLK must be the whole non fractional multiple of FOSC 3 Calculate the value of M to configure the MSEL bits M CCLK FOSC M must be in the range of 1 to 32 The value written to the MSEL bits in PLLCFG is M 1 see Table 23 4 Find a value for P to configure the PSEL bi...

Page 31: ...the oscillator is shut down and the chip receives no internal clocks The processor state and registers peripheral registers and internal SRAM values are preserved throughout Power down mode and the logic levels of chip pins remain static The Power down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks Since...

Page 32: ...t peripheral is enabled If a peripheral bit is 0 that peripheral is disabled to conserve power For example if bit 19 is 1 the I2C1 interface is enabled If bit 19 is 0 the I2C1 interface is disabled Important valid read from a peripheral register and valid write to a peripheral register is possible only if that peripheral is enabled in the PCONP register Table 24 Power control registers Name Descri...

Page 33: ... software should not write ones to reserved bits The value read from a reserved bit is not defined NA 1 PCTIM0 Timer Counter 0 power clock control bit 1 2 PCTIM1 Timer Counter 1 power clock control bit 1 3 PCUART0 UART0 power clock control bit 1 4 PCUART1 UART1 power clock control bit 1 6 5 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defi...

Page 34: ...or all subsequent resets when crystal oscillator is already running and stable signal is on the X1 pin the RESET pin needs to be asserted for 300 ns only When the internal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the Boot Block At that point all of the processor and peripheral registers have been initialized to predetermined value...

Page 35: ... 1 from APB Reset EINT0 wake up EINT1 wake up EINT2 wake up PLL Table 27 Reset Source identification Register RSIR address 0xE01F C180 bit description Bit Symbol Description Reset value 0 POR Power On Reset POR event sets this bit and clears all of the other bits in this register But if another Reset signal e g External Reset remains asserted after the POR signal is negated then its bit is set Thi...

Page 36: ...e APB Divider relative to the oscillator and the processor clock is shown in Figure 11 Because the APB Divider is connected to the PLL output the PLL remains active if it was running during Idle mode 3 11 1 Register description Only one register is used to control the APB Divider 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 3 11 2 APBDIV regist...

Page 37: ...existing ambient conditions Once a clock is detected the wake up timer counts 4096 clocks then enables the on chip circuitry to initialize When the onboard modules initialization is complete the processor is released to execute instructions if the external Reset has been deasserted In the case where an external clock source is used in the system as opposed to a crystal connected to the oscillator ...

Page 38: ...To summarize on the LPC2101 02 03 the wake up timer enforces a minimum reset duration based on the crystal oscillator and is activated whenever there is a wake up from Power down mode or any type of Reset 3 13 Code security vs debugging Applications in development typically need the debugging and tracing facilities in the LPC2101 02 03 Later in the life cycle of an application it may be more impor...

Page 39: ...the entire Flash line that contains it The MAM uses the LPROT 0 line to differentiate between instruction and data accesses Code and data accesses use separate 128 bit buffers 3 of every 4 sequential 32 bit code or data accesses hit in the buffer without requiring a Flash access 7 of 8 sequential 16 bit accesses 15 of every 16 sequential byte accesses The fourth eighth 16th sequential data access ...

Page 40: ...ollowing descriptions the term fetch applies to an explicit Flash read request from the ARM Pre fetch is used to denote a Flash read of instructions beyond the current processor fetch address 4 3 1 Flash memory bank There is one bank of Flash memory with the LPC2101 02 03 MAM Flash programming operations are not controlled by the MAM but are handled as a separate function A boot block sector conta...

Page 41: ...Flash programming or erase operation Any subsequent read from a Flash address will cause a new fetch to be initiated after the Flash operation has completed 4 4 MAM operating modes Three modes of operation are defined for the MAM trading off performance for ease of predictability Mode 0 MAM off All memory requests result in a Flash read operation see note 2 below There are no instruction prefetche...

Page 42: ...s Details of the registers appear in the description of each function 1 Reset value reflects the data stored in used bits only It does not include reserved bits content 4 7 MAM Control register MAMCR 0xE01F C000 Two configuration bits select the three MAM operating modes as shown in Table 33 Following Reset MAM functions are disabled Changing the MAM operating mode causes the MAM to invalidate all...

Page 43: ...ck faster than 40 MHz 3 CCLKs are proposed Table 33 MAM Control Register MAMCR address 0xE01F C000 bit description Bit Symbol Value Description Reset value 1 0 MAM_mode _control 00 MAM functions disabled 0 01 MAM functions partially enabled 10 MAM functions fully enabled 11 Reserved Not to be used in the application 7 2 Reserved user software should not write ones to reserved bits The value read f...

Page 44: ...es which FIQ source s is are requesting an interrupt Vectored IRQs have the middle priority but only 16 of the 32 requests can be assigned to this category Any of the 32 requests can be assigned to any of the 16 vectored IRQ slots among which slot 0 has the highest priority and slot 15 has the lowest Non vectored IRQs have the lowest priority The VIC ORs the requests from all the vectored and non ...

Page 45: ...uests from various peripheral functions R W 0 0xFFFF F018 VICSoftIntClear Software Interrupt Clear Register This register allows software to clear one or more bits in the Software Interrupt register WO 0 0xFFFF F01C VICProtection Protection enable register This register allows limiting access to the VIC registers by software running in privileged mode R W 0 0xFFFF F020 VICVectAddr Vector Address R...

Page 46: ... 15 each control one of the 16 vectored IRQ slots Slot 0 has the highest priority and slot 15 the lowest R W 0 0xFFFF F200 VICVectCntl1 Vector control 1 register R W 0 0xFFFF F204 VICVectCntl2 Vector control 2 register R W 0 0xFFFF F208 VICVectCntl3 Vector control 3 register R W 0 0xFFFF F20C VICVectCntl4 Vector control 4 register R W 0 0xFFFF F210 VICVectCntl5 Vector control 5 register R W 0 0xFF...

Page 47: ...the interrupt request with this bit number Writing zeroes to bits in VICSoftInt has no effect see VICSoftIntClear Section 5 4 2 0 1 Force the interrupt request with this bit number Table 38 Software Interrupt Clear register VICSoftIntClear address 0xFFFF F01C bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol TIMER3 TIMER2 Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18...

Page 48: ...O Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP SPI1 SPI0 I2C0 Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 WDT Access RO RO RO RO RO RO RO RO Table 41 Raw Interrupt status register VICRawIntr address 0xFFFF F008 bit description Bit Symbol Value Description Reset value 31 0 See VICRawIntr bit allocation table 0 The interrupt reque...

Page 49: ... to FIQ or IRQ zeroes have no effect See Section 5 4 5 Interrupt Enable Clear register VICIntEnClear 0xFFFF F014 on page 49 and Table 45 below for how to disable interrupts 0 Table 44 Software Interrupt Clear register VICIntEnClear address 0xFFFF F014 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol TIMER3 TIMER2 Access WO WO WO WO WO WO WO WO Bit 23 22 21 20 19 18 17 16 S...

Page 50: ... description Bit Symbol Value Description Reset value 31 0 See VICIntSelect bit allocation table 0 The interrupt request with this bit number is assigned to the IRQ category 0 1 The interrupt request with this bit number is assigned to the FIQ category Table 48 IRQ Status register VICIRQStatus address 0xFFFF F000 bit allocation Reset value 0x0000 0000 Bit 31 30 29 28 27 26 25 24 Symbol TIMER3 TIME...

Page 51: ...RO RO Bit 15 14 13 12 11 10 9 8 Symbol EINT1 EINT0 RTC PLL SSP SPI1 SPI0 I2C0 0 Access RO RO RO RO RO RO RO RO Bit 7 6 5 4 3 2 1 0 Symbol UART1 UART0 TIMER1 TIMER0 ARMCore1 ARMCore0 WDT Access RO RO RO RO RO RO RO RO Table 51 FIQ Status register VICFIQStatus address 0xFFFF F004 bit description Bit Symbol Description Reset value 31 0 See VICFIQStatus bit allocation table A bit read as 1 indicates a...

Page 52: ...ority such slot will be provided when the IRQ service routine reads the Vector Address register VICVectAddr Section 5 4 10 0x0000 0000 Table 54 Default Vector Address register VICDefVectAddr address 0xFFFF F034 bit description Bit Symbol Description Reset value 31 0 IRQ_vector When an IRQ service routine reads the Vector Address register VICVectAddr and no IRQ slot responds as described above this...

Page 53: ...0 2 CR0 CR1 CR2 4 0x0000 0010 TIMER1 Match 0 3 MR0 MR1 MR2 MR3 Capture 0 3 CR0 CR1 CR2 CR3 5 0x0000 0020 UART0 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI 6 0x0000 0040 UART1 Rx Line Status RLS Transmit Holding Register Empty THRE Rx Data Available RDA Character Time out Indicator CTI Modem Status Interrupt MSI 7 0x0000 0080 Reserv...

Page 54: ...HARDWARE PRIORITY LOGIC IRQSTATUS 31 0 nVICFIQ NonVectIRQ non vectored IRQ interrupt logic priority 0 nVICIRQ VECTADDR0 31 0 VECTIRQ1 VECTIRQ15 VECTADDR1 31 0 VECTADDR15 31 0 IRQ address select for highest priority interrupt VECTORADDR 31 0 VICVECT ADDROUT 31 0 DEFAULT VECTORADDR 31 0 priority14 priority15 priority2 priority1 VECTORADDR 31 0 SOURCE VECTORCNTL 5 0 ENABLE vector interrupt 0 vector i...

Page 55: ...ted code In this case the VIC will not be able to clearly identify the interrupt that generated the interrupt request and as a result the VIC will return the default interrupt VicDefVectAddr 0xFFFF F034 This potentially disastrous chain of events can be prevented in two ways 1 Application code should be set up in a way to prevent the spurious interrupts from occurring Simple guarding of changes to...

Page 56: ...t and therefore execution will continue with all interrupts disabled However this can cause problems in the following cases Problem 1 A particular routine maybe called as an IRQ handler or as a regular subroutine In the latter case the system guarantees that IRQs would have been disabled prior to the routine being called The routine exploits this restriction to determine how it was called by exami...

Page 57: ...ing of the IRQ handler As the required state of all bits in the c field of the CPSR are known this can be most efficiently be achieved by writing an immediate value to CPSR_C for example MSR cpsr_c I_Bit OR irq_MODE IRQ should be disabled FIQ enabled ARM state IRQ mode This requires only the IRQ handler to be modified and FIQs may be re enabled more quickly than by using workaround 1 However this ...

Page 58: ...0000 must be assigned Therefore writing 1 to any bit in Clear register will have one time effect in the destination register If the watchdog is enabled for interrupt on underflow or invalid feed sequence only then there is no way of clearing the interrupt The only way you could perform return from interrupt is by disabling the interrupt at the VIC using VICIntEnClr Example Assuming that UART0 and ...

Page 59: ...lume 1 Chapter 5 VIC In case UART0 request has been made VICVectAddr will be identical to VICVectAddr0 while in case SPI0 request has been made value from VICVectAddr1 will be found here If neither UART0 nor SPI0 have generated IRQ request but UART1 and or I2C were the reason content of VICVectAddr will be identical to VICDefVectAddr ...

Page 60: ...P0 9 RXD1 MAT2 2 P0 27 TRST CAP2 0 P0 8 TXD1 MAT2 1 P0 28 TMS CAP2 1 P0 7 SSEL0 MAT2 0 P0 29 TCK CAP2 2 DBGSEL X1 RTCK X2 RTXC2 P0 0 TXD0 MAT3 1 P0 18 CAP1 3 SDA1 P0 1 RXD0 MAT3 2 P0 17 CAP1 2 SCL1 P0 30 TDI MAT3 3 P0 16 EINT0 MAT0 2 P0 31 TDO P0 15 RI1 EINT2 V DD 3V3 P0 14 DCD1 SCK1 EINT1 P0 2 SCL0 CAP0 0 V SS V SS V DDA RTXC1 P0 13 DTR1 MAT1 1 P0 3 SDA0 MAT0 0 V DD 3V3 P0 4 SCK0 CAP0 1 P0 26 AD0...

Page 61: ...AD0 0 RTXC1 V SS P0 3 SDA0 MAT0 0 RST P0 4 SCK0 CAP0 1 VDD 1V8 P0 5 MISO0 MAT0 1 P0 21 SSEL1 MAT3 0 P0 6 MOSI0 CAP0 2 P0 20 MAT1 3 MOSI1 RTXC2 P0 19 MAT1 2 MISO1 DBGSEL P0 18 CAP1 3 SDA1 P0 7 SSEL0 MAT2 0 P0 17 CAP1 2 SCL1 P0 8 TXD1 MAT2 1 P0 16 EINT0 MAT0 2 P0 9 RXD1 MAT2 2 P0 15 RI1 EINT2 VSSA P0 14 DCD1 SCK1 EINT1 Table 58 Pin description Symbol LQFP48 PLCC44 Type Description P0 0 to P0 31 I O ...

Page 62: ...r Out Slave In for SPI0 Data output from SPI master or data input to SPI slave I CAP0 2 Capture input for Timer 0 channel 2 P0 7 SSEL0 MAT2 0 28 2 31 2 I O P0 7 General purpose Input output digital pin GPIO I SSEL0 Slave Select for SPI0 Selects the SPI interface as a slave O MAT2 0 PWM output for Timer 2 channel 0 P0 8 TXD1 MAT2 1 29 4 32 4 I O P0 8 General purpose Input output digital pin GPIO O ...

Page 63: ... 18 CAP1 3 SDA1 48 1 6 1 I O P0 18 General purpose Input output digital pin GPIO I CAP1 3 Capture input for Timer 1 channel 3 I O SDA1 I2C1 data Input output Open drain output for I2C bus compliance P0 19 MAT1 2 MISO1 1 1 7 1 I O P0 19 General purpose Input output digital pin GPIO O MAT1 2 PWM output for Timer 1 channel 2 I O MISO1 Master In Slave Out for SSP Data input to SPI master or data outpu...

Page 64: ...9 5 O Output from the RTC oscillator circuit RTCK 26 5 n c I O Returned test clock output Extra signal added to the JTAG port Assists debugger synchronization when processor frequency varies Bidirectional pin with internal pull up X1 11 16 I Input to the oscillator circuit and internal clock generator circuits X2 12 17 O Output from the oscillator amplifier DBGSEL 27 30 I Debug select When LOW the...

Page 65: ...h filter that blocks pulses shorter than 3 ns 3 Open drain 5 V tolerant digital I O I2C bus 400 kHz specification compatible pad It requires external pull up to provide an output functionality 4 5 V tolerant pad providing digital I O with TTL levels and hysteresis and 10 ns slew rate control and analog input function If configured for an input function this pad utilizes built in glitch filter that...

Page 66: ... exclusion is the case of inputs to the A D converter Regardless of the function that is currently selected for the port pin hosting the A D input this A D input can be read at any time and variations of the voltage level on this pin will be reflected in the A D readings However valid analog reading s can be obtained if and only if the function of an analog input is selected Only in this case the ...

Page 67: ...2 C000 PINSEL0 Pin name Value Function Value after reset 1 0 P0 0 0 0 GPIO Port 0 0 0 0 1 TXD0 UART0 1 0 MAT3 1 Timer 3 1 1 Reserved 3 2 P0 1 0 0 GPIO Port 0 1 0 0 1 RXD0 UART0 1 0 MAT3 2 Timer 3 1 1 Reserved 5 4 P0 2 0 0 GPIO Port 0 2 0 0 1 SCL0 I2C0 1 0 CAP0 0 Timer 0 1 1 Reserved 7 6 P0 3 0 0 GPIO Port 0 3 0 0 1 SDA0 I2C0 1 0 MAT0 0 Timer 0 1 1 Reserved 9 8 P0 4 0 0 GPIO Port 0 4 0 0 1 SCK0 SPI...

Page 68: ...1 Reserved 21 20 P0 10 0 0 GPIO Port 0 10 0 0 1 RTS1 UART1 1 0 CAP1 0 Timer 1 1 1 AD0 3 23 22 P0 11 0 0 GPIO Port 0 11 0 0 1 CTS1 UART1 1 0 CAP1 1 Timer 1 1 1 AD0 4 25 24 P0 12 0 0 GPIO Port 0 12 0 0 1 DSR1 UART1 1 0 MAT1 0 Timer 1 1 1 AD0 5 27 26 P0 13 0 0 GPIO Port 0 13 0 0 1 Reserved 1 0 MAT1 1 Timer 1 1 1 DTR1 UART1 29 28 P0 14 0 0 GPIO Port 0 14 0 0 1 EINT1 1 0 SCK1 SSP1 1 1 DCD1 UART1 31 30 ...

Page 69: ...0 0 GPIO Port 0 20 0 0 1 MOSI1 SPI1 1 0 MAT1 3 Timer 1 1 1 Reserved 11 10 P0 21 0 0 GPIO Port 0 21 0 0 1 SSEL1 SPI1 1 0 MAT3 0 Timer 3 1 1 Reserved 13 12 P0 22 0 0 GPIO Port 0 22 0 0 1 Reserved 1 0 Reserved 1 1 AD0 0 15 14 P0 23 0 0 GPIO Port 0 23 0 0 1 Reserved 1 0 Reserved 1 1 AD0 1 17 16 P0 24 0 0 GPIO Port 0 24 0 0 1 Reserved 1 0 Reserved 1 1 AD0 2 19 18 P0 25 0 0 GPIO Port 0 25 0 0 1 Reserved...

Page 70: ...r each pin Details for a specific derivative may be found in the appropriate data sheet 23 22 P0 27 0 0 GPIO Port 0 27 0 0 1 TRST JTAG 1 0 CAP2 0 Timer 2 1 1 Reserved 25 24 P0 28 0 0 GPIO Port 0 28 0 0 1 TMS JTAG 1 0 CAP2 1 Timer 2 1 1 Reserved 27 26 P0 29 0 0 GPIO Port 0 29 0 0 1 TCK JTAG 1 0 CAP2 2 Timer 2 1 1 Reserved 29 28 P0 30 0 0 GPIO Port 0 30 0 0 1 TDI JTAG 1 0 MAT3 3 Timer 3 1 1 Reserved...

Page 71: ...uts after reset Backward compatibility with other earlier devices is maintained with legacy registers appearing at the original addresses on the APB bus 8 2 Applications General purpose I O Driving LEDs or other indicators Controlling off chip devices Sensing digital inputs 8 3 Pin description 8 4 Register description LPC2101 02 03 has one 32 bit General Purpose I O port A total of 32 input output...

Page 72: ...ia the corresponding legacy register The following text will refer to the legacy GPIO as the slow GPIO while GPIO equipped with the enhanced features will be referred as the fast GPIO 1 Reset value reflects the data stored in used bits only It does not include reserved bits content Table 64 GPIO register map legacy APB accessible registers Generic Name Description Acces s Reset value 1 PORT0 Addre...

Page 73: ... R W 0x0000 0000 0x3FFF C010 FIO0MASK FIOPIN Fast GPIO Port Pin value register using FIOMASK The current state of digital port pins can be read from this register regardless of pin direction or alternate function selection as long as pins is not configured as an input to ADC The value read is masked by ANDing with FIOMASK Writing to this register places corresponding values in all bits enabled by ...

Page 74: ...led pin is input 0x0000 0000 1 Controlled pin is output Table 68 Fast GPIO port 0 Direction control byte and half word accessible register description Register name Register length bits access Address Description Reset value FIO0DIR0 8 byte 0x3FFF C000 Fast GPIO Port 0 Direction control register 0 Bit 0 in FIO0DIR0 register corresponds to P0 0 bit 7 to P0 7 0x00 FIO0DIR1 8 byte 0x3FFF C001 Fast GP...

Page 75: ...oth the IOSET and IOCLR registers to obtain the entire written value This feature should be used carefully in an application since it affects the entire port The legacy register is the IO0PIN while the enhanced GPIOs are supported via the FIO0PIN register Access to a port pins via the FIOPIN register is conditioned by the corresponding FIOMASK register see Section 8 4 2 Fast GPIO port 0 Mask regis...

Page 76: ...t GPIO port 0 Mask register FIOMASK Port 0 FIO0MASK 0x3FFF C010 Table 71 GPIO port 0 Pin value register IO0PIN address 0xE002 8000 bit description Bit Symbol Description Reset value 31 0 P0xVAL Slow GPIO pin value bits Bit 0 in IO0PIN corresponds to P0 0 Bit 31 in IO0PIN corresponds to P0 31 NA Table 72 Fast GPIO port 0 Pin value register FIO0PIN address 0x3FFF C014 bit description Bit Symbol Desc...

Page 77: ...nds to P0 0 Bit 31 in IO0SET corresponds to P0 31 0x0000 0000 Table 75 Fast GPIO port 0 output Set register FIO0SET address 0x3FFF C018 bit description Bit Symbol Description Reset value 31 0 FP0xSET Fast GPIO output value Set bits Bit 0 in FIO0SET corresponds to P0 0 Bit 31 in FIO0SET corresponds to P0 31 0x0000 0000 Table 76 Fast GPIO port 0 output Set byte and half word accessible register desc...

Page 78: ...final write to IO0CLR register sets pin P0 7 back to LOW level Table 78 Fast GPIO port 0 output Clear register 0 FIO0CLR address 0x3FFF C01C bit description Bit Symbol Description Reset value 31 0 FP0xCLR Fast GPIO output value Clear bits Bit 0 in FIO0CLR corresponds to P0 0 Bit 31 in FIO0CLR corresponds to P0 31 0x0000 0000 Table 79 Fast GPIO port 0 output Clear byte and half word accessible regi...

Page 79: ...evel at a time Only pin bit s in the IOSET IOCLR written with 1 will be set to HIGH LOW level while those written as 0 will remain unaffected However by just writing to either IOSET or IOCLR register it is not possible to instantaneously output arbitrary binary data containing mixture of 0s and 1s on a GPIO port Write to the IOPIN register enables instantaneous output of a desired content on the p...

Page 80: ...ibed in Section 4 9 MAM usage notes on page 43 Execution from the on chip SRAM is independent from the MAM setup set port 0 to slow GPIO ldr r0 0xe01fc1a0 register address SCS register mov r1 0x0 set bit 0 to 0 str r1 r0 enable slow port ldr r1 0xffffffff ldr r0 0xe0028008 register address IODIR str r1 r0 set port 0 to output ldr r2 0x00100000 select P0 20 ldr r0 0xe0028004 register address IOSET ...

Page 81: ... V 2006 All rights reserved User manual Rev 01 12 January 2006 81 Philips Semiconductors UM10161 Volume 1 Chapter 8 GPIO Fig 16 Illustration of the fast and slow GPIO access and output showing 3 5 x increase of the pin output frequency ...

Page 82: ...s Mechanism that enables software and hardware flow control implementation 9 2 Pin description 9 3 Register description UART0 contains registers organized as shown in Table 81 The Divisor Latch Access Bit DLAB is contained in U0LCR 7 and enables access to the Divisor Latches UM10161 Chapter 9 Universal Asynchronous Receiver Transmitter 0 UART0 Rev 01 12 January 2006 User manual Table 80 UART0 pin ...

Page 83: ... RO NA 0xE000 C000 DLAB 0 U0THR Transmit Holding Register 8 bit Write Data WO NA 0xE000 C000 DLAB 0 U0DLL Divisor Latch LSB 8 bit Data R W 0x01 0xE000 C000 DLAB 1 U0DLM Divisor Latch MSB 8 bit Data R W 0x00 0xE000 C004 DLAB 1 U0IER Interrupt Enable Register En ABTO En ABEO R W 0x00 0xE000 C004 DLAB 0 En RX Lin St Int Enable THRE Int En RX Dat Av Int U0IIR Interrupt ID Reg ABTO Int ABEO Int RO 0x01...

Page 84: ...U0LCR must be zero in order to access the U0THR The U0THR is always Write Only 9 3 3 UART0 Divisor Latch registers U0DLL 0xE000 C000 and U0DLM 0xE000 C004 when DLAB 1 The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock which must be 16x the desired baud ...

Page 85: ...ld comply to the following conditions 1 0 MULVAL 15 2 0 DIVADDVAL 15 Table 84 UART0 Divisor Latch LSB register U0DLL address 0xE000 C000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLL The UART0 Divisor Latch LSB Register along with the U0DLM register determines the baud rate of the UART0 0x01 Table 85 UART0 Divisor Latch MSB register U0DLM address 0xE000 C004 when DLAB 1 bi...

Page 86: ...t system with PCLK 20 MHz U0DL 130 U0DLM 0x00 and U0DLL 0x82 DIVADDVAL 0 and MULVAL 1 will enable UART0 with UART0baudrate 9615 bauds Example 2 Using UART0baudrate formula from above it can be determined that system with PCLK 20 MHz U0DL 93 U0DLM 0x00 and U0DLL 0x5D DIVADDVAL 2 and MULVAL 5 will enable UART0 with UART0baudrate 9600 bauds UART0baudrate PCLK 16 16 U0DLM U0DLL MulVal MulVal DivAddVal...

Page 87: ...rates available when using 20 MHz peripheral clock PCLK 20 MHz Desired baudrate MULVAL 0 DIVADDVAL 0 Optimal MULVAL DIVADDVAL U0DLM U0DLL error 3 U0DLM U0DLL dec 1 Fractional pre scaler value MULDIV MULDIV DIVADDVAL error 3 hex 2 dec 1 Table 88 UART0 Interrupt Enable Register U0IER address 0xE000 C004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR Interrupt Enable 0 U0I...

Page 88: ...e read from a reserved bit is not defined NA Table 88 UART0 Interrupt Enable Register U0IER address 0xE000 C004 when DLAB 0 bit description Bit Symbol Value Description Reset value Table 89 UART0 Interrupt Identification Register UOIIR address 0xE000 C008 read only bit description Bit Symbol Value Description Reset value 0 Interrupt Pending 0 Note that U0IIR 0 is active LOW The pending interrupt c...

Page 89: ...and 1 to 5 CTI interrupts depending on the service routine resulting in the transfer of the remaining 5 characters 1 Values 0000 0011 0101 0111 1000 1001 1010 1011 1101 1110 1111 are reserved 2 For details see Section 9 3 10 UART0 Line Status Register U0LSR 0xE000 C014 Read Only 3 For details see Section 9 3 1 UART0 Receiver Buffer register U0RBR 0xE000 C000 when DLAB 0 Read Only 4 For details see...

Page 90: ...Reset value 0 FIFO Enable 0 UART0 FIFOs are disabled Must not be used in the application 0 1 Active HIGH enable for both UART0 Rx and TX FIFOs and U0FCR 7 1 access This bit must be set for proper UART0 operation Any transition on this bit will automatically clear the UART0 FIFOs 1 RX FIFO Reset 0 No impact on either of UART0 FIFOs 0 1 Writing a logic 1 to U0FCR 1 will clear all bytes in UART0 Rx F...

Page 91: ...able access to Divisor Latches Table 92 UART0 Line Control Register U0LCR address 0xE000 C00C bit description Bit Symbol Value Description Reset value Table 93 UART0 Line Status Register U0LSR address 0xE000 C014 read only bit description Bit Symbol Value Description Reset value 0 Receiver Data Ready RDR 0 U0LSR0 is set when the U0RBR holds an unread character and is cleared when the UART0 RBR FIF...

Page 92: ... Once the break condition has been detected the receiver goes idle until RXD0 goes to marking state all 1 s An U0LSR read clears this status bit The time of break detection is dependent on U0FCR 0 Note The break interrupt is associated with the character at the top of the UART0 RBR FIFO 0 Break interrupt status is inactive 1 Break interrupt status is active 5 Transmitter Holding Register Empty THR...

Page 93: ... falling edge of the start bit and the falling edge of the least significant bit In mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART0 Rx pin the length of the start bit Table 95 Auto baud Control Register U0ACR 0xE000 C020 bit description Bit Symbol Value Description Reset value 0 Start This bit is automatically cleared after auto baud completion...

Page 94: ... before U0ACR register write The minimum and the maximum baudrates supported by UART0 are function of PCLK number of data bits stop bits and parity bits 3 9 3 14 UART0 Transmit Enable Register U0TER 0xE000 C030 LPC2101 02 03 s U0TER enables implementation of software flow control When TXEn 1 UART0 transmitter will keep sending data as long as they are available As soon as TXEn becomes 0 UART0 tran...

Page 95: ...ge on UART0 Rx pin triggers the beginning of the start bit The rate measuring counter will start counting PCLK cycles optionally pre scaled by the fractional baud rate generator 3 During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the fractional baud rate pre scaled UART0 input clock guaranteeing the start bit is stored in the U0RSR 4 During the...

Page 96: ...lid characters via RXD0 After a valid character is assembled in the U0RSR it is passed to the UART0 RX Buffer Register FIFO to await access by the CPU or host via the generic host interface a Mode 0 start bit and LSB are used for auto baud b Mode 1 only start bit is used for auto baud Fig 17 Autobaud a mode 0 and b mode 1 waveform UART0 RX start bit LSB of A or a U0ACR start rate counter start bit...

Page 97: ...e serial output pin TXD0 The UART0 Baud Rate Generator block U0BRG generates the timing enables used by the UART0 TX block The U0BRG clock input source is the APB clock PCLK The main clock is divided down per the divisor specified in the U0DLL and U0DLM registers This divided down clock is a 16x oversample clock NBAUDOUT The interrupt interface contains registers U0IER and U0IIR The interrupt inte...

Page 98: ...2006 98 Philips Semiconductors UM10161 Volume 1 Chapter 9 UART0 Fig 18 UART0 block diagram APB INTERFACE U0LCR U0RX DDIS U0LSR U0FCR U0BRG U0TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR PCLK U0INTR U0SCR NTXRDY TXD0 NBAUDOUT RCLK NRXRDY RXD0 U0RBR U0RSR U0DLM U0DLL U0THR U0TSR U0IIR U0IER ...

Page 99: ...R 0 and is a source for a priority level 4 interrupt if enabled U1IER 3 1 DCD1 Input Data Carrier Detect Active LOW signal indicates if the external modem has established a communication link with the UART1 and data may be exchanged In normal operation of the modem interface U1MCR 4 0 the complement value of this signal is stored in U1MSR 7 State change information is stored in U1MSR3 and is a sou...

Page 100: ...LL Divisor Latch LSB 8 bit Data R W 0x01 0xE001 0000 DLAB 1 U1DLM Divisor Latch MSB 8 bit Data R W 0x00 0xE001 0004 DLAB 1 U1IER Interrupt Enable Register En ABTO En ABEO R W 0x00 0xE001 0004 DLAB 0 En CTS Int E Modem St Int En RX Lin St Int Enable THRE Int En RX Dat Av Int U1IIR Interrupt ID Reg ABTO Int ABEO Int RO 0x01 0xE001 0008 FIFOs Enabled IIR3 IIR2 IIR1 IIR0 U1FCR FIFO Control Register RX...

Page 101: ...CR must be zero in order to access the U1THR The U1THR is always Write Only 10 3 3 UART1 Divisor Latch registers 0 and 1 U1DLL 0xE001 0000 and U1DLM 0xE001 0004 when DLAB 1 The UART1 Divisor Latch is part of the UART1 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional prescaler in order to produce the baud rate clock which must be 16x the desired...

Page 102: ... comply to the following conditions 1 0 MULVAL 15 2 0 DIVADDVAL 15 Table 101 UART1 Divisor Latch LSB register U1DLL address 0xE001 0000 when DLAB 1 bit description Bit Symbol Description Reset value 7 0 DLLSB The UART1 Divisor Latch LSB Register along with the U1DLM register determines the baud rate of the UART1 0x01 Table 102 UART1 Divisor Latch MSB register U1DLM address 0xE001 0004 when DLAB 1 ...

Page 103: ...at system with PCLK 20 MHz U1DL 130 U1DLM 0x00 and U1DLL 0x82 DIVADDVAL 0 and MULVAL 1 will enable UART1 with UART1baudrate 9615 bauds Example 2 Using UART1baudrate formula from above it can be determined that system with PCLK 20 MHz U1DL 93 U1DLM 0x00 and U1DLL 0x5D DIVADDVAL 2 and MULVAL 5 will enable UART1 with UART1baudrate 9600 bauds UART1baudrate PCLK 16 16 U1DLM U1DLL MulVal MulVal DivAddVa...

Page 104: ... peripheral clock PCLK 20 MHz Desired baudrate MULVAL 0 DIVADDVAL 0 Optimal MULVAL DIVADDVAL U1DLM U1DLL error 3 U1DLM U1DLL dec 1 Fractional pre scaler value MULDIV MULDIV DIVADDVAL error 3 hex 2 dec 1 Table 105 UART1 Interrupt Enable Register U1IER address 0xE001 0004 when DLAB 0 bit description Bit Symbol Value Description Reset value 0 RBR Interrupt Enable 0 U1IER 0 enables the Receive Data Av...

Page 105: ...Interrupt unless the interrupt has been disabled by clearing the U1IER 3 bit in the U1IER register In auto CTS mode a transition on the CTS1 bit will trigger an interrupt only if both the U1IER 3 and U1IER 7 bits are set 0 0 Disable the CTS interrupt 1 Enable the CTS interrupt 8 ABTOIntEn 0 U1IER8 enables the auto baud time out interrupt Disable Auto baud Time out Interrupt 0 1 Enable Auto baud Ti...

Page 106: ...occurred in 3 5 to 4 5 character times Any UART1 Rx FIFO activity read or write of UART1 RSR will clear the interrupt This interrupt is intended to flush the UART1 RBR after a message has been received that is not a multiple of the trigger level size For example if a peripheral wished to send a 105 character message and the trigger level was 10 characters the CPU would receive 10 RDA interrupts re...

Page 107: ...HR FIFO has held two or more characters at one time and currently the U1THR is empty The THRE interrupt is reset when a U1THR write occurs or a read of the U1IIR occurs and the THRE is the highest interrupt U1IIR 3 1 001 The modem interrupt U1IIR 3 1 000 is available in LPC2104 05 06 It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins DCD DS...

Page 108: ...bytes in UART1 TX FIFO and reset the pointer logic This bit is self clearing 5 3 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 7 6 RX Trigger Level 00 These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated 0 trigger level 0 1 character or 0x01 01 trigger level 1 4 charact...

Page 109: ...1 RTS Control Source for modem output pin RTS This bit reads as 0 when modem loopback mode is active 0 3 2 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 4 Loopback Mode Select 0 The modem loopback mode provides a mechanism to perform diagnostic loopback testing Serial data from the transmitter is connected internally to serial in...

Page 110: ...ART1 operating in type 550 has trigger level in U1FCR set to 0x2 then if auto RTS is enabled the UART1 will deassert the RTS1 output as soon as the receive FIFO contains 8 bytes see Table 108 on page 108 The RTS1 output will be reasserted as soon as the receive FIFO hits the previous trigger level 4 bytes Auto CTS The auto CTS function is enabled by setting the CTSen bit If auto CTS is enabled the...

Page 111: ...y register that provides status information on the UART1 TX and RX blocks 1 0 x x 1 yes 1 1 0 x 0 no 1 1 0 x 1 yes 1 1 1 0 0 no 1 1 1 1 x yes 1 1 1 x 1 yes Table 111 Modem status interrupt generation Enable Modem Status Interrupt U1IER 3 CTSen U1MCR 7 CTS Interrupt Enable U1IER 7 Delta CTS U1MSR 0 Delta DCD or Trailing Edge RI or Delta DSR U1MSR 3 or U1MSR 2 or U1MSR 1 Modem Status Interrupt Fig 2...

Page 112: ...racter at the top of the UART1 RBR FIFO 0 Framing error status is inactive 1 Framing error status is active 4 Break Interrupt BI 0 When RXD1 is held in the spacing state all 0 s for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all 1 s An U1LSR read clears this statu...

Page 113: ...detected on modem input DSR 2 Trailing Edge RI 0 Set upon LOW to HIGH transition of input RI Cleared on an U1MSR read 0 No change detected on modem input RI 1 LOW to HIGH transition detected on RI 3 Delta DCD 0 Set upon state change of input DCD Cleared on an U1MSR read 0 No change detected on modem input DCD 1 State change detected on modem input DCD 4 CTS Clear To Send State Complement of input ...

Page 114: ... counter overflows If this bit is set the rate measurement will restart at the next falling edge of the UART1 Rx pin The auto baud function can generate two interrupts The U1IIR ABTOInt interrupt will get set if the interrupt is enabled U1IER ABToIntEn is set and the auto baud rate measurement counter overflows The U1IIR ABEOInt interrupt will get set if the interrupt is enabled U1IER ABEOIntEn is...

Page 115: ...is set the auto baud protocol will execute the following phases 1 On U1ACR Start bit setting the baud rate measurement counter is reset and the UART1 U1RSR is reset The U1RSR baud rate is switch to the highest rate 2 A falling edge on UART1 Rx pin triggers the beginning of the start bit The rate measuring counter will start counting PCLK cycles optionally pre scaled by the fractional baud rate gen...

Page 116: ...s TXEn becomes 0 UART1 transmission will stop Table 116 describes how to use TXEn bit in order to achieve software flow control a Mode 0 start bit and LSB are used for auto baud b Mode 1 only start bit is used for auto baud Fig 21 Autobaud a mode 0 and b mode 1 waveform UART1 RX start bit LSB of A or a U1ACR start rate counter start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop A 0x41 or a 0...

Page 117: ...modem interface contains registers U1MCR and U1MSR This interface is responsible for handshaking between a modem peripheral and the UART1 The interrupt interface contains registers U1IER and U1IIR The interrupt interface receives several one clock wide enables from the U1TX and U1RX blocks Status information from the U1TX and U1RX is stored in the U1LSR Control information for the U1TX and U1RX is...

Page 118: ...onductors UM10161 Volume 1 Chapter 10 UART1 Fig 22 UART1 block diagram APB INTERFACE U1LCR U1RX DDIS U1LSR U1FCR U1BRG U1TX INTERRUPT PA 2 0 PSEL PSTB PWRITE PD 7 0 AR MR PCLK U1INTR U1SCR NTXRDY TXD1 NBAUDOUT RCLK NRXRDY RXD1 U1RBR U1RSR U1DLM U1DLL U1THR U1TSR U1IIR U1IER MODEM RTS U1MCR U1MSR DTR DCD RI DSR CTS ...

Page 119: ...ess Next follows a number of data bytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes othe...

Page 120: ...ossible slave operation is not interrupted If bus arbitration is lost in the master mode the I2C block switches to the slave mode immediately and can detect its own slave address in the same serial transfer 11 5 1 Master Transmitter mode In this mode data is transmitted from master to slave Before the master transmitter mode can be entered the I2CONSET register must be initialized as shown in Tabl...

Page 121: ...s set again and the possible status codes now are 0x18 0x20 or 0x38 for the master mode or 0x68 0x78 or 0xB0 if the slave mode was enabled by setting AA to 1 The appropriate actions to be taken for each of these status codes are shown in Table 133 to Table 136 11 5 2 Master Receiver mode In the master receiver mode data is received from a slave transmitter The transfer is initiated in the same way...

Page 122: ...data direction bit If the direction bit is 0 W it enters slave receiver mode If the direction bit is 1 R it enters slave transmitter mode After the address and direction bit have been received the SI bit is set and a valid status code can be read from the Status register I2STAT Refer to Table 135 for the status codes and actions Fig 25 Format of Master Receiver mode Fig 26 A Master Receiver switch...

Page 123: ...red so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I2C interface switches to the slave mode immediately and can detect its own slave address in the same serial transfer 11 6 I2C implementation and operation Figure 29 shows how the on chip I2C bus interface is implemented and the following text describes the individual blocks 11 6 1 Input filter...

Page 124: ...rm to the I2C specification Fig 29 I2C serial interface block diagram APB BUS STATUS REGISTER CONTROL REGISTER SCL DUTY CYCLE REGISTERS ADDRESS REGISTER COMPARATOR SHIFT REGISTER 8 8 ACK I2ADR I2DAT 8 16 BIT COUNTER ARBITRATION SYNC LOGIC SERIAL CLOCK GENERATOR TIMING CONTROL LOGIC STATUS DECODER status bus I2CONSET I2SCLL I2SCLH I2CONCLR interrupt PCLK INPUT FILTER OUTPUT STAGE SCL INPUT FILTER O...

Page 125: ...n from master transmitter to slave receiver is made with the correct data in I2DAT 11 6 5 Arbitration and synchronization logic In the master transmitter mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the I2C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the I2C block immediately changes fr...

Page 126: ...ster transmitter or master receiver mode It is switched off when the I2C block is in a slave mode The I2C output clock frequency and duty cycle is programmable via the I2C Clock Control Registers See the description of the I2CSCLL and I2CSCLH registers for details The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above...

Page 127: ...ed by software The three least significant bits of the status register are always zero If the status code is used as a vector to service routines then the routines are displaced by eight address locations Eight bytes of code is sufficient for most of the service routines see the software example in this section 11 7 Register description Each I2C interface contains 7 registers as shown in Table 120...

Page 128: ...T condition if it is already in master mode I2SCLH SCH Duty Cycle Register High Half Word Determines the high time of the I2C clock R W 0x04 0xE001 C010 I2C0SCLH 0xE005 C010 I2C1SCLH I2SCLL SCL Duty Cycle Register Low Half Word Determines the low time of the I2C clock I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode R W 0x04...

Page 129: ... automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode The STO flag is cleared by hardware automatically SI is the I2C Interrupt Flag This bit is set when the I2C state changes However entering state F...

Page 130: ... Status register is Read Only The three least significant bits are always 0 Taken as a byte the status register contents represent a status code There are 26 possible status codes When the status code is 0xF8 there is no relevant information available and the SI bit is not set All other 25 status codes correspond to defined I2C states When any of these states entered the SI bit will be set For a c...

Page 131: ...I2C0 I2C0SCLL 0xE001 C014 I2C1 I2C1SCLL 0xE0015 C014 11 7 8 Selecting the appropriate I2C data rate and duty cycle Software must set values for the registers I2SCLH and I2SCLL to select the appropriate data rate and duty cycle I2SCLH defines the number of PCLK cycles for the SCL HIGH time I2SCLL defines the number of PCLK cycles for the SCL low time The frequency is determined by the following for...

Page 132: ...SCLL and I2SCLH values 11 8 Details of I2C operating modes The four operating modes are Master Transmitter Master Receiver Slave Receiver Slave Transmitter Data transfers in each mode of operation are shown in Figure 32 Figure 33 Figure 34 Figure 35 and Figure 36 Table 129 lists abbreviations used in these figures when describing the I2C operating modes Table 128 Example I2C clock rates I2SCLL I2S...

Page 133: ... the bus In other words if AA is reset the I2C interface cannot enter a slave mode STA STO and SI must be reset The master transmitter mode may now be entered by setting the STA bit The I2C logic will now test the I2C bus and generate a start condition as soon as the bus becomes free When a START condition is transmitted the serial interrupt flag SI is set and the status code in the status registe...

Page 134: ...To initiate the slave receiver mode I2ADR and I2CON must be loaded as follows The upper 7 bits are the address to which the I2C block will respond when addressed by a master If the LSB GC is set the I2C block will respond to the general call address 0x00 otherwise it ignores the general call address The I2C bus rate settings do not affect the I2C block in the slave mode I2EN must be set to logic 1...

Page 135: ... transfer the I2C block will return a not acknowledge logic 1 to SDA after the next received data byte While AA is reset the I2C block does not respond to its own slave address or a general call address However the I2C bus is still monitored and address recognition may be resumed at any time by setting AA This means that the AA bit may be used to temporarily isolate the I2C block from the I2C bus ...

Page 136: ...s Other Master continues A Other Master continues 20H 08H 18H 28H 30H 10H 68H 78H B0H 38H 38H Arbitration lost in Slave Address or Data byte Not Acknowledge received after a Data byte Not Acknowledge received after the Slave Address Next transfer started with a Repeated Start condition Arbitration lost and addressed as Slave Successful transmission to a Slave Receiver From Master to Slave From Sla...

Page 137: ...tinues Other Master continues A Other Master continues 48H 40H 58H 10H 68H 78H B0H 38H 38H Arbitration lost in Slave Address or Acknowledge bit Not Acknowledge received after the Slave Address Next transfer started with a Repeated Start condition Arbitration lost and addressed as Slave Successful transmission to a Slave Transmitter From Master to Slave From Slave to Master Any number of data bytes...

Page 138: ...lost as Master and addressed as Slave Last data byte received is Not Acknowledged Arbitration lost as Master and addressed as Slave by General Call Reception of the own Slave Address and one or more Data bytes all are acknowledged From Master to Slave From Slave to Master Any number of data bytes and their associated Acknowledge bits n This number contained in I2STA corresponds to a defined state ...

Page 139: ...ock is in the master mode see state 0xB0 If the AA bit is reset during a transfer the I2C block will transmit the last byte of the transfer and enter state 0xC0 or 0xC8 The I2C block is switched to the not addressed slave mode and will ignore the master receiver if it continues the transfer Thus the master receiver receives all 1s as serial data While AA is reset the I2C block does not respond to ...

Page 140: ... be transmitted ACK bit will be received No I2DAT action or 1 0 0 X Repeated START will be transmitted No I2DAT action or 0 1 0 X STOP condition will be transmitted STO flag will be reset No I2DAT action 1 1 0 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x28 Data byte in I2DAT has been transmitted ACK has been received Load data byte or 0 0 0 X Data by...

Page 141: ... R has been transmitted ACK has been received No I2DAT action or 0 0 0 0 Data byte will be received NOT ACK bit will be returned No I2DAT action 0 0 0 1 Data byte will be received ACK bit will be returned 0x48 SLA R has been transmitted NOT ACK has been received No I2DAT action or 1 0 0 X Repeated START condition will be transmitted No I2DAT action or 0 1 0 X STOP condition will be transmitted STO...

Page 142: ...0 0 Data byte will be received and NOT ACK will be returned No I2DAT action X 0 0 1 Data byte will be received and ACK will be returned 0x80 Previously addressed with own SLV address DATA has been received ACK has been returned Read data byte or X 0 0 0 Data byte will be received and NOT ACK will be returned Read data byte X 0 0 1 Data byte will be received and ACK will be returned 0x88 Previously...

Page 143: ...if I2ADR 0 logic 1 A START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX No STDAT action or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No STDAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized Gene...

Page 144: ...ion or 0 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address No I2DAT action or 0 0 0 1 Switched to not addressed SLV mode Own SLA will be recognized General call address will be recognized if I2ADR 0 logic 1 No I2DAT action or 1 0 0 0 Switched to not addressed SLV mode no recognition of own SLA or General call address A START condition will be transmitted wh...

Page 145: ...r 11 8 7 I2STAT 0x00 This status code indicates that a bus error has occurred during an I2C serial transfer A bus error is caused when a START or STOP condition occurs at an illegal position in the format frame Examples of such illegal positions are during the serial transfer of an address byte a data byte or an acknowledge bit A bus error may also be caused when external interference disturbs the...

Page 146: ...aster receiver modes see Figure 30 Loss of arbitration is indicated by the following states in I2STAT 0x38 0x68 0x78 and 0xB0 see Figure 32 and Figure 33 If the STA flag in I2CON is set by the routines which service these states then if the bus is free again a START condition state 0x08 is transmitted without intervention by the CPU and a retry of the total serial transfer can commence 11 8 11 For...

Page 147: ...cause the SDA line is pulled LOW while the I2C bus is considered free The I2C hardware attempts to generate a START condition after every two additional clock pulses on the SCL line When the SDA line is eventually released a normal START condition is transmitted state 0x08 is entered and the serial transfer continues If a forced bus access occurs or a repeated START condition is transmitted while ...

Page 148: ...transmission and reception The initialization routine performs the following functions I2ADR is loaded with the part s own slave address and the general call bit GC The I2C interrupt enable and interrupt priority bits are set The slave mode is enabled by simultaneously setting the I2EN and AA bits in I2CON and the serial clock frequency for master modes is defined by loading CR0 and CR1 in I2CON T...

Page 149: ...s long as care is taken that the those states can never occur In an application it may be desirable to implement some kind of timeout during I2C operations in order to trap an inoperative bus or a lost service routine 11 9 Software example 11 9 1 Initialization routine Example to initialize I2C Interface as a Slave and or Master 1 Load I2ADR with own Slave Address enable general call recognition i...

Page 150: ...bus 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 5 2 Master States State 08 and State 10 are for both Master Transmit and Master Receive modes The R W bit decides whether the next state is within Master Transmit mode or Master Receive mode 11 9 5 3 State 0x08 A Start condition has been transmitted The Slave Address R W bit will be tr...

Page 151: ...s been transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 6 3 State 0x28 Data has been transmitted ACK has been received If the transmitted data was the last data byte then transmit a Stop condition otherwise transmit the next data byte 1 Decrement the Master data c...

Page 152: ... Address Read has been transmitted NOT ACK has been received A Stop condition will be transmitted 1 Write 0x14 to I2CONSET to set the STO and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 7 3 State 0x50 Data has been received ACK has been returned Data will be read from I2DAT Additional data will be received If this is the last data byte then NOT ACK will be returned otherwise ...

Page 153: ...d STA is set to restart Master mode after the bus is free again 1 Write 0x24 to I2CONSET to set the STA and AA bits 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Set up Slave Receive mode data buffer 4 Initialize Slave data counter 5 Exit 11 9 8 3 State 0x70 General call has been received ACK has been returned Data will be received and ACK returned 1 Write 0x04 to I2CONSET to set the AA bit 2 Wr...

Page 154: ...sed Slave mode is entered 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit 11 9 8 7 State 0x90 Previously addressed with general call Data has been received ACK has been returned Received data will be saved Only the first data byte will be received with ACK Additional data will be received with NOT ACK 1 Read data byte from I2DAT into the Slave Receiv...

Page 155: ...be received STA is set to restart Master mode after the bus is free again 1 Load I2DAT from Slave Transmit buffer with first data byte 2 Write 0x24 to I2CONSET to set the STA and AA bits 3 Write 0x08 to I2CONCLR to clear the SI flag 4 Set up Slave Transmit mode data buffer 5 Increment Slave Transmit buffer pointer 6 Exit 11 9 9 3 State 0xB8 Data has been transmitted ACK has been received Data will...

Page 156: ...cs N V 2006 All rights reserved User manual Rev 01 12 January 2006 156 Philips Semiconductors UM10161 Volume 1 Chapter 11 I2C interfaces 1 Write 0x04 to I2CONSET to set the AA bit 2 Write 0x08 to I2CONCLR to clear the SI flag 3 Exit ...

Page 157: ...f data to the master 12 2 2 SPI data transfers Figure 39 is a timing diagram that illustrates the four different data transfer formats that are available with the SPI This timing diagram illustrates a single 8 bit data transfer The first thing you should notice in this timing diagram is that it is divided into three horizontal parts The first part describes the SCK and SSEL signals The second part...

Page 158: ...he clock and begin the transfer The transfer ends when the last clock cycle of the transfer is complete Fig 39 SPI data transfer format CPHA 0 and CPHA 1 MISO CPHA 1 MOSI CPHA 1 Cycle CPHA 1 CPHA 1 MISO CPHA 0 MOSI CPHA 0 Cycle CPHA 0 CPHA 0 SSEL SCK CPOL 1 SCK CPOL 0 1 2 3 8 7 6 5 4 BIT 1 BIT 2 BIT 3 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 1 BIT 2 BIT 3 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 1 2 3 8 7 6 5 4 BIT...

Page 159: ...ransmit case There is no buffer between the data register and the internal shift register A write to the data register goes directly into the internal shift register Therefore data should only be written to this register when a transmit is not currently in progress Read data is buffered When a transfer is complete the receive data is transferred to a single byte data buffer where it is later read ...

Page 160: ... is required to transmit Note that a read or write of the SPI data register is required in order to clear the SPIF status bit Therefore at least one of the optional reads or writes of the SPI data register must take place in order to clear the SPIF status bit 12 2 6 Exception conditions 12 2 7 Read overrun A read overrun occurs when the SPI block internal read buffer contains data that has not bee...

Page 161: ... other time it is either in its inactive state or tri stated SSEL0 Input Slave Select The SPI slave select signal is an active LOW signal that indicates which slave is currently selected to participate in a data transfer Each slave has its own unique slave select signal input The SSEL must be LOW before data transactions begin and normally stays LOW for the duration of the transaction If the SSEL ...

Page 162: ...T SPI Interrupt Flag This register contains the interrupt flag for the SPI interface R W 0x00 0xE002 001C Table 141 SPI Control Register S0SPCR address 0xE002 0000 bit description Bit Symbol Value Description Reset value 1 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 2 BitEnable 0 The SPI controller sends and receives 8 bits o...

Page 163: ...ble 142 SPI Status Register S0SPSR address 0xE002 0004 bit description Bit Symbol Description Reset value 2 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 3 ABRT Slave abort When 1 this bit indicates that a slave abort has occurred This bit is cleared by reading this register 0 4 MODF Mode fault when 1 this bit indicates that a ...

Page 164: ... SPI Interrupt register S0SPINT 0xE002 001C This register contains the interrupt flag for the SPI0 interface 12 5 Architecture The block diagram of the SPI solution implemented in SPI0 interface is shown in the Figure 40 Table 143 SPI Data Register S0SPDR address 0xE002 0008 bit description Bit Symbol Description Reset value 7 0 DataLow SPI Bi directional data port 0x00 15 8 DataHigh If bit 2 of t...

Page 165: ... Philips Semiconductors UM10161 Volume 1 Chapter 12 SPI Fig 40 SPI block diagram MOSI_IN MOSI_OUT MISO_IN MISO_OUT OUTPUT ENABLE LOGIC SPI REGISTER INTERFACE SPI Interrupt APB Bus SPI SHIFT REGISTER SCK_OUT_EN MOSI_OUT_EN MISO_OUT_EN SCK_IN SCK_OUT SS_IN SPI STATE CONTROL SPI CLOCK GENERATOR DETECTOR ...

Page 166: ...inciple full duplex with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data UM10161 Chapter 13 SSP Controller SPI1 Rev 01 12 January 2006 User manual Table 146 SSP pin descriptions Pin Name Type Interface pin name function Pin Description SPI SSI Microwire SC...

Page 167: ...ct signal from the Master can be connected directly to the slave s corresponding input When there is more than one slave on the bus further qualification of their Frame Select Slave Select inputs will typically be necessary to prevent more than one slave from responding to a transfer MISO1 I O MISO DR M DX S SI M SO S Master In Slave Out The MISO signal transfers serial data from the slave to the ...

Page 168: ...e falling edge of each CLK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched 13 3 2 SPI frame format The SPI interface is a four wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the...

Page 169: ...iods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being driven LOW This causes slave data to be enabled onto the MISO input line of the master Master s MOSI is enabled One half SCK period later valid master data ...

Page 170: ...equence for SPI format with CPOL 0 CPHA 1 is shown in Figure 43 which covers both single and continuous transfers In this configuration during idle periods The CLK signal is forced LOW SSEL is forced HIGH The transmit MOSI MISO pad is in high impedance If the SSP is enabled and there is valid data within the transmit FIFO the start of transmission is signified by the SSEL master signal being drive...

Page 171: ...Now that both the master and slave data have been set the SCK master clock pin becomes LOW after one further half SCK period This means that data is captured on the falling edges and be propagated on the rising edges of the SCK signal In the case of a single word transmission after all bits of the data word are transferred the SSEL line is returned to its idle HIGH state one SCK period after the l...

Page 172: ...is enabled After a further one half SCK period both master and slave data are enabled onto their respective transmission lines At the same time the SCK is enabled with a falling edge transition Data is then captured on the rising edges and propagated on the falling edges of the SCK signal After all bits have been transferred in the case of a single word transmission the SSEL line is returned to it...

Page 173: ...for the duration of the frame transmission The SI pin remains tristated during this transmission The off chip serial slave device latches each control bit into its serial shifter on the rising edge of each SK After the last bit is latched by the slave device the control byte is decoded during a one clock wait state and the slave responds by transmitting data back to the SSP Each bit is driven onto...

Page 174: ...strates these setup and hold time requirements With respect to the SK rising edge on which the first bit of receive data is to be sampled by the SSP slave CS must have a setup of at least two times the period of SK on which the SSP operates With respect to the SK rising edge previous to this edge CS must have a hold of at least one SK period 13 4 Register description The SSP contains 9 registers a...

Page 175: ... 0x03 0xE006 800C SSPCPSR Clock Prescale Register R W 0x00 0xE006 8010 SSPIMSC Interrupt Mask Set and Clear Register R W 0x00 0xE006 8014 SSPRIS Raw Interrupt Status Register R W 0x04 0xE006 8018 SSPMIS Masked Interrupt Status Register RO 0x00 0xE006 801C SSPICR SSPICR Interrupt Clear Register WO NA 0xE006 8020 Table 148 SSP Control Register 0 SSPCR0 address 0xE006 8000 bit description Bit Symbol ...

Page 176: ...R 1 0x00 Table 148 SSP Control Register 0 SSPCR0 address 0xE006 8000 bit description Bit Symbol Value Description Reset value Table 149 SSP Control Register 1 SSPCR1 address 0xE006 8004 bit description Bit Symbol Value Description Reset value 0 LBM 0 Loop Back Mode During normal operation 0 1 Serial input is taken from the serial output MOSI or MISO rather than the serial input pin MISO or MOSI re...

Page 177: ... length is less than 16 bits software must right justify the data written to this register Read software can read data from this register whenever the RNE bit in the Status register is 1 indicating that the Rx FIFO is not empty When software reads this register the SSP controller returns data from the least recent frame in the Rx FIFO If the data length is less than 16 bits the data is right justi...

Page 178: ...he Rx FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 0 1 RTIM Software should set this bit to enable interrupt when a Receive Timeout condition occurs A Receive Timeout occurs when the Rx FIFO is not empty and no new data has been received nor has data been read from the FIFO for 32 bit ...

Page 179: ...ess 0xE006 801C bit description Bit Symbol Description Reset value 0 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full and this interrupt is enabled 0 1 RTMIS This bit is 1 when there is a Receive Timeout condition and this interrupt is enabled Note that a Receive Timeout can be negated if further data is received 0 2 RXMIS This bit is 1 if the Rx FIFO is at l...

Page 180: ... input signals Note that these analog inputs are always connected to their pins even if the Pin function Select register assigns them to port pins A simple self test of the ADC can be done by driving these pins as port outputs Note if the ADC is used signal levels on analog input pins must not be above the level of V3A at any time Otherwise A D converter readings will be invalid If the A D convert...

Page 181: ...ontributing to the generation of an A D interrupt R W 0x0000 0100 0xE003 400C AD0INTEN ADDR0 A D Channel 0 Data Register This register contains the result of the most recent conversion completed on channel 0 RO NA 0xE003 4010 AD0DR0 ADDR1 A D Channel 1 Data Register This register contains the result of the most recent conversion completed on channel 1 RO NA 0xE003 4014 AD0DR1 ADDR2 A D Channel 2 D...

Page 182: ...ns at the rate selected by the CLKS field scanning if necessary through the pins selected by 1s in the SEL field The first conversion after the start corresponds to the least significant 1 in the SEL field then higher numbered 1 bits pins if applicable Repeated conversions can be terminated by clearing this bit but the conversion that s in progress when this bit is cleared will be completed Import...

Page 183: ...lue Description Reset value Table 160 A D Global Data Register AD0GDR address 0xE003 4004 bit description Bit Symbol Description Reset value 5 0 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 15 6 RESULT When DONE is 1 this field contains a binary fraction representing the voltage on the Ain pin selected by the SEL field divided b...

Page 184: ...rs the DONE status flag from the result register for A D channel 5 0 6 DONE6 This bit mirrors the DONE status flag from the result register for A D channel 6 0 7 DONE7 This bit mirrors the DONE status flag from the result register for A D channel 7 0 8 OVERRUN0 This bit mirrors the OVERRRUN status flag from the result register for A D channel 0 0 9 OVERRUN1 This bit mirrors the OVERRRUN status fla...

Page 185: ... interrupt 0 1 Completion of a conversion on ADC channel 7 will generate an interrupt 8 ADGINTEN 0 Only the individual ADC channels enabled by ADINTEN7 0 will generate interrupts 1 1 Only the global DONE flag in ADDR is enabled to generate an interrupt 31 9 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 162 A D Status Regist...

Page 186: ... bit 27 is used in the edge detection logic 14 5 2 Interrupts An interrupt request is asserted to the Vectored Interrupt Controller VIC when the DONE bit is 1 Software can use the Interrupt Enable bit for the A D Converter in the VIC to control whether this assertion results in an interrupt DONE is negated when the ADDR is read 14 5 3 Accuracy vs digital receiver The AD0 function must be selected ...

Page 187: ... capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM ouputs 15 2 Applications Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer Pulse Width Modulator via Match outputs 15 3 ...

Page 188: ...CAP0 2 0 CAP1 3 0 Input Capture Signals A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt Here is the list of all CAPTURE signals together with pins on where they can be selected CAP0 0 P0 2 CAP0 1 P0 4 CAP0 2 P0 6 CAP1 0 P0 10 CAP1 1 P0 11 CAP1 2 P0 17 CAP1 3 P0 18 Timer Counter block can s...

Page 189: ...e and controllable through the bus interface R W 0 0xE000 4010 T0PC 0xE000 8010 T1PC MCR Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs R W 0 0xE000 4014 T0MCR 0xE000 8014 T1MCR MR0 Match Register 0 MR0 can be enabled through the MCR to reset the TC stop both the TC and PC and or generate an interrupt every time MR0 matches...

Page 190: ...1 02 03 R W 0 0xE000 403C T0EMR 0xE000 803C T1EMR CTCR Count Control Register The CTCR selects between Timer and Counter mode and in Counter mode selects the signal and edge s for counting R W 0 0xE000 4070 T0CTCR 0xE000 8070 T1CTCR PWMCON PWM Control Register The PWMCON enables PWM mode for the external match pins MAT0 3 0 and MAT1 3 0 R W 0 0xE000 4074 PWM0CON 0xE000 8074 PWM1CON Table 165 TIMER...

Page 191: ...lf of the PCLK clock Consequently duration of the HIGH LOWLOW levels on the same CAP input in this case can not be shorter than 1 PCLK Table 167 Timer Control Register TCR TIMER0 T0TCR address 0xE000 4004 and TIMER1 T1TCR address 0xE000 8004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the Timer Counter and Prescale Counter are enabled for counting When zero the cou...

Page 192: ...gister the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 15 5 7 Match Registers MR0 MR3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be triggered automatically The action possibilities are to generate an in...

Page 193: ... 0 0 Feature disabled 3 MR1I 1 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 0 This interrupt is disabled 4 MR1R 1 Reset on MR1 the TC will be reset if MR1 matches it 0 0 Feature disabled 5 MR1S 1 Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches the TC 0 0 Feature disabled 6 MR2I 1 Interrupt on MR2 an interrupt is generated whe...

Page 194: ...ure on CAPn 0 rising edge a sequence of 0 then 1 on CAPn 0 will cause CR0 to be loaded with the contents of TC 0 0 This feature is disabled 1 CAP0FE 1 Capture on CAPn 0 falling edge a sequence of 1 then 0 on CAPn 0 will cause CR0 to be loaded with the contents of TC 0 0 This feature is disabled 2 CAP0I 1 Interrupt on CAPn 0 event a CR0 load due to a CAPn 0 event will generate an interrupt 0 0 This...

Page 195: ...0xE000 803C bit description Bit Symbol Description Reset value 0 EM0 External Match 0 This bit reflects the state of output MAT0 0 MAT1 0 whether or not this output is connected to its pin When a match occurs between the TC and MR0 this output of the timer can either toggle go LOW go HIGH or do nothing Bits EMR 5 4 control the functionality of this output 0 1 EM1 External Match 1 This bit reflects...

Page 196: ...s the encoding of these bits 00 15 12 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 171 External Match Register EMR TIMER0 T0EMR address 0xE000 403C and TIMER1 T1EMR address0xE000 803C bit description Bit Symbol Description Reset value Table 172 External match control EMR 11 10 EMR 9 8 EMR 7 6 or EMR 5 4 Function 00 Do Noth...

Page 197: ... its reset value and will stay HIGH continuously Note When the match outputs are selected to perform as PWM outputs the timer reset MRnR and timer stop MRnS bits in the Match Control Register MCR must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit to one to enable the timer reset when the timer value matches the value of the correspondi...

Page 198: ...COUNTER0 and TIMER COUNTER1 is shown in Figure 52 Fig 50 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled PCLK prescale counter interrupt timer counter timer counter reset 2 2 2 2 0 0 0 0 1 1 1 1 4 5 6 0 1 Fig 51 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled PCLK prescale counter interrupt timer counter TCR 0 counter enable 2 ...

Page 199: ...imer0 1 block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 3 1 CAPTURE REGISTER 2 CAPTURE REGISTER 1 CAPTURE REGISTER 0 MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 CAPTURE CONTROL REGISTER CONTROL TIMER COUNTER CSN TCI CE INTERRUPT REGISTER EXTERNAL MATCH REGISTER MATCH CONTROL REGISTER MAT 3 0 INTERRUPT CAP 3 0...

Page 200: ...ggle on match Do nothing on match For each timer up to four match registers can be configured as PWM allowing to use up to three match outputs as single edge controlled PWM ouputs 16 2 Applications Interval Timer for counting internal events Pulse Width Demodulator via Capture inputs Free running timer Pulse Width Modulator via Match outputs 16 3 Description The Timer Counter is designed to count ...

Page 201: ...cription Pin Type Description CAP2 2 0 Input Capture Signals A transition on a capture pin can be configured to load one of the Capture Registers with the value in the Timer Counter and optionally generate an interrupt Here is the list of all CAPTURE signals together with pins on where they can be selected CAP2 0 P0 27 CAP2 1 P0 28 CAP2 2 P0 29 Timer Counter block can select a capture signal as a ...

Page 202: ... is cleared The PC is observable and controllable through the bus interface R W 0 0xE007 0010 T2PC 0xE007 4010 T3PC MCR Match Control Register The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs R W 0 0xE007 0014 T2MCR 0xE007 4014 T3MCR MR0 Match Register 0 MR0 can be enabled through the MCR to reset the TC stop both the TC and PC and or generate an i...

Page 203: ... 03 R W 0 0xE007 003C T2EMR 0xE007 403C T3EMR CTCR Count Control Register The CTCR selects between Timer and Counter mode and in Counter mode selects the signal and edge s for counting R W 0 0xE007 0070 T2CTCR 0xE007 4070 T3CTCR PWMCON PWM Control Register The PWMCON enables PWM mode for the external match pins MAT2 3 0 and MAT3 3 0 R W 0 0xE007 0074 PWM0CON 0xE007 4074 PWM1CON Table 175 TIMER COU...

Page 204: ...alf of the PCLK clock Consequently duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 PCLK Table 177 Timer Control Register TCR TIMER2 T2TCR address 0xE007 0004 and TIMER3 T3TCR address 0xE007 4004 bit description Bit Symbol Description Reset value 0 Counter Enable When one the Timer Counter and Prescale Counter are enabled for counting When zero the count...

Page 205: ...nted on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 16 5 7 Match Registers MR0 MR3 The Match register values are continuously compared to the Timer Counter value When the two values are equal actions can be ...

Page 206: ... 0 0 Feature disabled 3 MR1I 1 Interrupt on MR1 an interrupt is generated when MR1 matches the value in the TC 0 0 This interrupt is disabled 4 MR1R 1 Reset on MR1 the TC will be reset if MR1 matches it 0 0 Feature disabled 5 MR1S 1 Stop on MR1 the TC and PC will be stopped and TCR 0 will be set to 0 if MR1 matches the TC 0 0 Feature disabled 6 MR2I 1 Interrupt on MR2 an interrupt is generated whe...

Page 207: ...tion Bit Symbol Value Description Reset value 0 CAP0RE 1 Capture on CAPn 0 rising edge a sequence of 0 then 1 on CAPn 0 will cause CR0 to be loaded with the contents of TC 0 0 This feature is disabled 1 CAP0FE 1 Capture on CAPn 0 falling edge a sequence of 1 then 0 on CAPn 0 will cause CR0 to be loaded with the contents of TC 0 0 This feature is disabled 2 CAP0I 1 Interrupt on CAPn 0 event a CR0 l...

Page 208: ...is bit reflects the state of output MAT2 2 MAT3 2 whether or not this output is connected to its pin When a match occurs between the TC and MR2 this output of the timer can either toggle go LOW go HIGH or do nothing Bits EMR 9 8 control the functionality of this output 0 3 EM3 External Match 3 This bit reflects the state of output MAT2 3 MAT3 3 whether or not this output is connected to its pin Wh...

Page 209: ...than the PWM cycle length the PWM output remains continuously LOW 3 If a match value larger than the PWM cycle length is written to the match register and the PWM signal is HIGH already then the PWM signal will be cleared on the next timer reset 4 If a match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tic...

Page 210: ... timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value Figure 55 shows a timer configured to stop and generate an interrupt on match The prescaler is again set to 2 and the match register set to 6 In the next clock after the t...

Page 211: ...ors UM10161 Volume 1 Chapter 16 Timer2 and Timer3 16 9 Architecture The block diagram for TIMER COUNTER2 and TIMER COUNTER3 is shown in Figure 56 Fig 55 A timer cycle in which PR 2 MRx 6 and both interrupt and stop on match are enabled PCLK prescale counter interrupt timer counter TCR 0 counter enable 2 2 0 0 1 4 5 6 1 0 ...

Page 212: ...6 Timer2 3 block diagram reset MAXVAL TIMER CONTROL REGISTER PRESCALE REGISTER PRESCALE COUNTER PCLK enable CAPTURE REGISTER 2 1 CAPTURE REGISTER 1 1 CAPTURE REGISTER 0 1 MATCH REGISTER 3 MATCH REGISTER 2 MATCH REGISTER 1 MATCH REGISTER 0 CAPTURE CONTROL REGISTER CONTROL TIMER COUNTER CSN TCI CE INTERRUPT REGISTER EXTERNAL MATCH REGISTER MATCH CONTROL REGISTER MATn 3 0 INTERRUPT CAP2 2 0 STOP ON M...

Page 213: ...for measuring time when system power is on and optionally when it is off It uses little power in Power down mode On the LPC2101 02 03 the RTC can be clocked by a separate 32 768 KHz oscillator or by a programmable prescale divider based on the APB clock Also the RTC is powered by its own power supply pin VBAT which can be connected to a battery or to the same 3 3 V supply used by the rest of the d...

Page 214: ...dress ILR 2 Interrupt Location Register R W 0xE002 4000 CTC 15 Clock Tick Counter RO 0xE002 4004 CCR 4 Clock Control Register R W 0xE002 4008 CIIR 8 Counter Increment Interrupt Register R W 0xE002 400C AMR 8 Alarm Mask Register R W 0xE002 4010 CTIME0 32 Consolidated Time Register 0 RO 0xE002 4014 CTIME1 32 Consolidated Time Register 1 RO 0xE002 4018 CTIME2 32 Consolidated Time Register 2 RO 0xE002...

Page 215: ... 3 Interrupt Wake up register INTWAKE 0xE01F C144 on page 20 and Section 3 12 Wake up timer on page 37 17 4 2 Miscellaneous register group Table 185 summarizes the registers located from 0 to 7 of A 6 2 More detailed descriptions follow 17 4 3 Interrupt Location Register ILR 0xE002 4000 The Interrupt Location Register is a 2 bit register that specifies which blocks are generating an interrupt see ...

Page 216: ...o reserved bits The value read from a reserved bit is not defined NA Table 187 Clock Tick Counter Register CTC address 0xE002 4004 bit description Bit Symbol Description Reset value 14 0 Clock Tick Counter Prior to the Seconds counter the CTC counts 32 768 clocks per second Due to the RTC Prescaler these 32 768 time increments may not all be of the same duration Refer to the Section 17 6 Reference...

Page 217: ...xE002 4014 The Consolidated Time Register 0 contains the low order time values Seconds Minutes Hours and Day of Week Table 189 Counter Increment Interrupt Register CIIR address 0xE002 400C bit description Bit Symbol Description Reset value 0 IMSEC When 1 an increment of the Second value generates an interrupt NA 1 IMMIN When 1 an increment of the Minute value generates an interrupt NA 2 IMHOUR Whe...

Page 218: ...erved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA 26 24 Day Of Week Day of week value in the range of 0 to 6 NA 31 27 Reserved user software should not write ones to reserved bits The value read from a reserved bit is not defined NA Table 192 Consolidated Time register 1 CTIME1 address 0xE002 4018 bit description Bit Symbol Description ...

Page 219: ... Alarm Mask Register AMR 0xE002 4010 on page 217 alarm registers match their corresponding time counters then an interrupt is generated The interrupt is cleared when a one is written to bit one of the Interrupt Location Register ILR 1 Table 194 Time counter relationships and values Counter Size Enabled by Minimum value Maximum value Second 6 Clk1 see Figure 57 0 59 Minute 6 Second 0 59 Hour 5 Minu...

Page 220: ...rce is switched between the PCLK and the RTXC pins Once the 32 kHz signal from RTXC1 2 pins is selected as a clock source the RTC can operate completely without the presence of the APB clock PCLK Therefore power sensitive applications i e battery powered application utilizing the RTC will reduce the power consumption by using the signal from RTXC1 2 pins and writing a 0 into the PCRTC bit in the P...

Page 221: ...ed as PREFRAC PCLK PREINT 1 32768 17 6 3 Example of prescaler usage In a simplistic case the PCLK frequency is 65 537 kHz So PREINT int PCLK 32768 1 1 and PREFRAC PCLK PREINT 1 32768 1 With this prescaler setting exactly 32 768 clocks per second will be provided to the RTC by counting 2 PCLKs 32 767 times and 3 PCLKs once In a more realistic case the PCLK frequency is 10 MHz Then Table 197 Referen...

Page 222: ...e among the remaining pulses this jitter could possibly be of concern in an application that wishes to observe the contents of the Clock Tick Counter CTC directly Section 17 4 4 Clock Tick Counter Register CTC 0xE002 4004 on page 216 17 6 4 Prescaler operation The Prescaler block labelled Combination Logic in Figure 58 determines when the decrement of the 13 bit PREINT counter is extended by one P...

Page 223: ...nting the fraction 1 4 will cause every fourth cycle whenever the two LSBs of the Fraction Counter 10 counted by the 13 bit counter to be longer 17 7 RTC external 32 kHz oscillator component selection The RTC external oscillator circuit is shown in Figure 59 Since the feedback resistance is integrated on chip only a crystal the capacitances CX1 and CX2 need to be connected externally to the microc...

Page 224: ...of the crystal compared to the specified one Therefore for an accurate time reference it is advised to use the load capacitors as specified in Table 201 that belong to a specific CL The value of external capacitances CX1 and CX2 specified in this table are calculated from the internal parasitic capacitances and the CL Parasitics from PCB and package are not taken into account Fig 59 RTC 32 kHz cry...

Page 225: ...please read Section 3 10 Reset on page 33 of this document 18 3 Description The watchdog consists of a divide by 4 fixed pre scaler and a 32 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is 0xFF Setting a value lower than 0xFF causes 0xFF to be loaded in the counter Hence the minimum watchdog interva...

Page 226: ...hdog register map Name Description Access Reset value 1 Address WDMOD Watchdog Mode register This register contains the basic mode and status of the Watchdog Timer R W 0 0xE000 0000 WDTC Watchdog Timer Constant register This register determines the time out value R W 0xFF 0xE000 0004 WDFEED Watchdog Feed sequence register Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer to...

Page 227: ...therwise the watchdog is triggered The interrupt reset will be generated during the second PCLK following an incorrect access to a watchdog timer register during a feed sequence 18 4 4 Watchdog Timer Value register WDTV 0xE000 000C The WDTV register is used to read the current value of watchdog timer 18 5 Block diagram The block diagram of the Watchdog is shown below in the Figure 60 Table 204 Wat...

Page 228: ... is set and a valid feed sequence is done 2 WDEN and WDRESET are sticky bits Once set they can t be cleared until the watchdog underflows or an external reset occurs Fig 60 Watchdog block diagram PLCK WDTV register underflow WDRESET 2 WDINT WDTOF WDEN 2 WDMOD register reset interrupt SHADOW BIT enable count 1 32 BIT DOWN COUNTER CURRENT WD TIMER COUNT 4 WDFEED WDTC feed ok feed error feed sequence...

Page 229: ...st to start the ISP command handler Assuming that proper signal is present on X1 pin when the rising edge on RESET pin is generated it may take up to 3 ms before P0 14 is sampled and the decision on whether to continue with user code or ISP handler is made If P0 14 is sampled LOW and the watchdog overflow flag is set the external hardware request to start the ISP command handler is ignored If ther...

Page 230: ...ry point of the user application code If the signature is not valid the auto baud routine synchronizes with the host via serial port 0 The host should send a 0x3F as a synchronization character and wait for a response The host side serial port settings should be 8 data bits 1 stop bit and no parity The auto baud routine measures the bit time of the received synchronization character in terms of it...

Page 231: ...s are sent as CR LF terminated ASCII strings Data is sent and received in UU encoded format 19 4 4 ISP command format Command Parameter_0 Parameter_1 Parameter_n CR LF Data Data only for Write commands 19 4 5 ISP response format Return_Code CR LF Response_0 CR LF Response_1 CR LF Response_n CR LF Data Data only for Read commands 19 4 6 ISP data format The data stream is in UU encode format The UU ...

Page 232: ...isable interrupts or ensure that user interrupt vectors are active in RAM and that the interrupt handlers reside in RAM before making a flash erase write IAP call The IAP code does not use or disable interrupts 19 4 11 RAM used by ISP command handler ISP commands use on chip RAM from 0x4000 0120 to 0x4000 01FF The user could use this area but the contents may be lost upon reset Flash programming c...

Page 233: ...orrespondence between sector numbers and memory addresses for LPC2101 02 03 devices containing 8 16 and 32 kB of Flash respectively IAP ISP and RealMonitor routines are located in the boot block The boot block is present 1 Code Read Protection Fig 62 Boot process flowchart RUN AUTO BAUD RUN ISP COMMAND HANDLER RECEIVE CRYSTAL FREQUENCY no EXECUTE INTERNAL USER CODE yes AUTO BAUD SUCCESSFUL yes USE...

Page 234: ...Flash bytes from 0x0000 0000 to 0x0000 0003 are protected by the first ECC byte Flash bytes from 0x0000 0004 to 0x0000 0007 are protected by the second ECC byte etc Whenever the CPU requests a read from user s Flash both 128 bits of raw data containing the specified memory location and the matching ECC byte are evaluated If the ECC mechanism detects a single error in the fetched data a correction ...

Page 235: ... the device has gone through a power cycle 19 8 ISP commands The following commands are accepted by the ISP command handler Detailed status codes are supported for each command The command handler sends the return code INVALID_COMMAND when an undefined command is received Commands and return codes are in ASCII format CMD_SUCCESS is sent by ISP command handler only when received ISP command has bee...

Page 236: ...lock flash Write Erase and Go commands Example U 23130 CR LF unlocks the flash Write Erase Go commands Table 211 ISP Set Baud Rate command Command B Input Baud Rate 9600 19200 38400 57600 115200 230400 Stop bit 1 2 Return Code CMD_SUCCESS INVALID_BAUD_RATE INVALID_STOP_BIT PARAM_ERROR Description This command is used to change the baud rate The new baud rate is effective after the command handler ...

Page 237: ...ransmitting 20 UU encoded lines The checksum is generated by adding raw data before UU encoding bytes and is reset after transmitting 20 UU encoded lines The length of any UU encoded line should not exceed 61 characters bytes i e it can hold 45 data bytes When the data fits in less then 20 UU encoded lines then the check sum is of actual number of bytes sent The host should compare it with the che...

Page 238: ...coded ADDR_ERROR Address not on word boundary ADDR_NOT_MAPPED COUNT_ERROR Byte count is not a multiple of 4 PARAM_ERROR CODE_READ_PROTECTION_ENABLED Description This command is used to read data from RAM or Flash memory This command is blocked when code read protection is enabled Example R 1073741824 4 CR LF reads 4 bytes of data from address 0x4000 0000 Table 216 ISP Prepare sector s for write op...

Page 239: ...This command is used to program the flash memory The Prepare Sector s for Write Operation command should precede this command The affected sectors are automatically protected again once the copy command is successfully executed The boot block cannot be written by this command This command is blocked when code read protection is enabled Example C 0 1073774592 512 CR LF copies 512 bytes from the RAM...

Page 240: ...tors when the code read protection is enabled Example E 2 3 CR LF erases the flash sectors 2 and 3 Table 220 ISP Blank check sector command Command I Input Start Sector Number End Sector Number Should be greater than or equal to start sector number Return Code CMD_SUCCESS SECTOR_NOT_BLANK followed by Offset of the first non blank word location Contents of non blank word location INVALID_SECTOR PAR...

Page 241: ...OMPARE_ERROR Followed by the offset of first mismatch COUNT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED PARAM_ERROR Description This command is used to compare the memory contents at two locations Compare result may not be correct when source or destination address contains any of the first 64 bytes starting from address zero First 64 bytes are re mapped to flash boot sector...

Page 242: ... be called in the following way using C Define the IAP location entry point Since the 0th bit of the IAP location is set there will be a change to Thumb instruction set when the program counter branches to this address define IAP_LOCATION 0x7ffffff1 Define data structure or pointers to pass IAP command table and result table to the IAP function unsigned long command 5 6 COUNT_ERROR Byte count is n...

Page 243: ...Wed May 08 16 12 23 2002 0x7fffff90 T rm_init_entry 0x7fffffa0 A rm_undef_handler 0x7fffffb0 A rm_prefetchabort_handler 0x7fffffc0 A rm_dataabort_handler 0x7fffffd0 A rm_irqhandler 0x7fffffe0 A rm_irqhandler2 0x7ffffff0 T iap_entry As per the ARM specification The ARM Thumb Procedure Call Standard SWS ESPC 0002 A 05 up to 4 parameters can be passed in the r0 r1 r2 and r3 registers respectively Add...

Page 244: ...able 228 Erase sector s 5210 Table 229 Blank check sector s 5310 Table 230 Read Part ID 5410 Table 231 Read Boot code version 5510 Table 232 Compare 5610 Table 233 Reinvoke ISP 5710 Table 234 Fig 63 IAP Parameter passing COMMAND CODE PARAMETER 1 PARAMETER 2 PARAMETER n STATUS CODE RESULT 1 RESULT 2 RESULT n command parameter table command result table ARM REGISTER r0 ARM REGISTER r1 Table 227 IAP ...

Page 245: ...Copy RAM to Flash Input Command code 5110 Param0 DST Destination Flash address where data bytes are to be written This address should be a 256 byte boundary Param1 SRC Source RAM address from which data bytes are to be read This address should be a word boundary Param2 Number of bytes to be written Should be 256 512 1024 4096 Param3 System Clock Frequency CCLK in kHz Return Code CMD_SUCCESS SRC_AD...

Page 246: ...e same Start and End sector numbers Table 230 IAP Blank check sector s command Command Blank check sector s Input Command code 5310 Param0 Start Sector Number Param1 End Sector Number should be greater than or equal to start sector number Return Code CMD_SUCCESS BUSY SECTOR_NOT_BLANK INVALID_SECTOR Result Result0 Offset of the first non blank word location if the Status Code is SECTOR_NOT_BLANK Re...

Page 247: ...NT_ERROR Byte count is not a multiple of 4 ADDR_ERROR ADDR_NOT_MAPPED Result Result0 Offset of the first mismatch if the Status Code is COMPARE_ERROR Description This command is used to compare the memory contents at two locations The result may not be correct when the source or destination includes any of the first 64 bytes starting from address zero The first 64 bytes can be re mapped to RAM Tab...

Page 248: ...urce address is not on a word boundary 3 DST_ADDR_ERROR Destination address is not on a correct boundary 4 SRC_ADDR_NOT_MAPPED Source address is not mapped in the memory map Count value is taken in to consideration where applicable 5 DST_ADDR_NOT_MAPPED Destination address is not mapped in the memory map Count value is taken in to consideration where applicable 6 COUNT_ERROR Byte count is not mult...

Page 249: ...re two JTAG style scan chains within the ARM7TDMI S A JTAG style Test Access Port Controller controls the scan chains In addition to the scan chains the debug architecture uses EmbeddedICE logic which resides on chip with the ARM7TDMI S core The EmbeddedICE has its own scan chain that is used to insert watchpoints and breakpoints for the ARM7TDMI S core The EmbeddedICE logic consists of two real t...

Page 250: ...plexed pins On the LPC2101 02 03 the pins TMS TCK TDI TDO AND TRST are multiplexed with P0 27 P0 31 To have them come up as a Debug port connect a weak bias resistor 4 7 10 kΩ depending on the external JTAG circuitry between VSS and the RTCK pin To Table 236 EmbeddedICE pin description Pin Name Type Description TMS Input Test Mode Select The TMS pin selects the next state in the TAP state machine ...

Page 251: ...sable interrupts 00000 Debug Status 5 Status of debug 00001 Debug Comms Control Register 32 Debug communication control register 00100 Debug Comms Data Register 32 Debug communication data register 00101 Watchpoint 0 Address Value 32 Holds watchpoint 0 address value 01000 Watchpoint 0 Address Mask 32 Holds watchpoint 0 address mask 01001 Watchpoint 0 Data Value 32 Holds watchpoint 0 data value 010...

Page 252: ...l times see Figure 65 For debugging with JTAG pins RTCK must be HIGH as the RST pin is released see Figure 66 RTCK may be driven HIGH externally or allowed to float HIGH via its on chip pull up The RTCK output driver is disabled until the internal wake up time has expired Fig 64 EmbeddedICE debug environment block diagram ARM7TDMI S TARGET BOARD EMBEDDED ICE INTERFACE PROTOCOL CONVERTER EMBEDDED I...

Page 253: ...verride related to DBGSEL and RTCK see Table 58 in Section 6 2 Pin description for LPC2101 02 03 on page 61 20 8 2 JTAG pin selection The Primary JTAG port can be selected for debugging only when DBGSEL and RTCK pins are HIGH at reset see Figure 66 If at least one of the DBGSEL or RTCK lines is LOW at reset JTAG will not be enabled and can not be used for later debugging 1 DBGSEL must be HIGH 2 RT...

Page 254: ...sent in the EmbeddedICE logic RealMonitor provides advantages over the traditional methods for debugging applications in ARM systems The traditional methods include Angel a target based debug monitor Multi ICE or other JTAG unit and EmbeddedICE logic a hardware based debug solution Although both of these methods provide robust debugging environments neither is suitable as a lightweight real time m...

Page 255: ...hown in Figure 67 RealMonitor is split in to two functional components 21 3 2 RMHost This is located between a debugger and a JTAG unit The RMHost controller RealMonitor dll converts generic Remote Debug Interface RDI requests from the debugger into DCC only RDI messages for the JTAG unit For complete details on debugging a RealMonitor integrated application from the host see the ARM RMHost User G...

Page 256: ...e host component RMHost using the Debug Communications Channel DCC which is a reliable link whose data is carried over the JTAG connection While the user application is running RMTarget typically uses IRQs generated by the DCC This means that if the user application also wants to use IRQs it must pass any DCC generated interrupts to RealMonitor To allow nonstop debugging the EmbeddedICE RT logic i...

Page 257: ...tion Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped 21 4 How to enable Realmonitor The following steps must be performed to enable RealMonitor A code example which implements all the steps can be found at the end of this section 21 4 1 Adding stacks User must ensure that stacks are set up within application for ...

Page 258: ... interrupts and exceptions Figure 69 illustrates how exceptions can be claimed by RealMonitor itself or shared between RealMonitor and application If user application requires the exception sharing they must provide function such as app_IRQDispatch Depending on the nature of the exception this handler can either Pass control to the RealMonitor processing routine such as rm_irqhandler2 Claim the ex...

Page 259: ...nit_entry IMPORT rm_prefetchabort_handler IMPORT rm_dataabort_handler IMPORT rm_irqhandler2 IMPORT rm_undef_handler IMPORT User_Entry Entry point of user application CODE32 ENTRY Define exception table Instruct linker to place code at address 0x0000 0000 AREA exception_table CODE LDR pc Reset_Address LDR pc Undefined_Address LDR pc SWI_Address LDR pc Prefetch_Address LDR pc Abort_Address Fig 69 Ex...

Page 260: ... CODE ram_end EQU 0x4000xxxx Top of on chip RAM __init Set up the stack pointers for various processor modes Stack grows downwards LDR r2 ram_end Get top of RAM MRS r0 CPSR Save current processor mode Initialize the Undef mode stack for RealMonitor use BIC r1 r0 0x1f ORR r1 r1 0x1b MSR CPSR_c r1 Keep top 32 bytes for flash programming routines Refer to Flash Memory System and Programming chapter S...

Page 261: ... 0xC0 enable IRQs and FIQs MSR CPSR_c r1 update the CPSR Get the address of the User entry point LDR lr User_Entry MOV pc lr Non vectored irq handler app_irqDispatch AREA app_irqDispatch CODE VICVectAddrOffset EQU 0x30 app_irqDispatch enable interrupt nesting STMFD sp r12 r14 MRS r12 spsr Save SPSR in to r12 MSR cpsr_c 0x1F Re enable IRQ go to system mode User should insert code here if non vector...

Page 262: ...channel RM_OPT_STOPSTART TRUE This option enables or disables support for all stop and start debugging features RM_OPT_SOFTBREAKPOINT TRUE This option enables or disables support for software breakpoints RM_OPT_HARDBREAKPOINT TRUE Enabled for cores with EmbeddedICE RT This device uses ARM 7TDMI S Rev 4 with EmbeddedICE RT RM_OPT_HARDWATCHPOINT TRUE Enabled for cores with EmbeddedICE RT This device...

Page 263: ...OPT_GATHER_STATISTICS FALSE This option enables or disables the code for gathering statistics about the internal operation of RealMonitor RM_DEBUG FALSE This option enables or disables additional debugging and error checking code in RealMonitor RM_OPT_BUILDIDENTIFIER FALSE This option determines whether a build identifier is built into the capabilities table of RMTarget Capabilities table is store...

Page 264: ...ronics N V 2006 All rights reserved User manual Rev 01 12 January 2006 264 Philips Semiconductors UM10161 Volume 1 Chapter 21 RealMonitor This option allows RMTarget to support vector chaining through µHAL ARM HW abstraction API ...

Page 265: ...onym Description ADC Analog to Digital Converter CPU Central Processing Unit DAC Digital to Analog Converter DCC Debug Communications Channel FIFO First In First Out GPIO General Purpose Input Output NA Not Applicable PLL Phase Locked Loop PWM Pulse Width Modulator RAM Random Access Memory SRAM Static Random Access Memory UART Universal Asynchronous Receiver Transmitter VIC Vector Interrupt Contro...

Page 266: ...escription 21 Table 12 External Interrupt Polarity register EXTPOLAR address 0xE01F C14C bit description 22 Table 13 System Control and Status flags register SCS address 0xE01F C1A0 bit description 23 Table 14 Memory Mapping control register MEMMAP address 0xE01F C040 bit description 23 Table 15 PLL registers 25 Table 16 PLL Control register PLLCON address 0xE01F C080 bit description 27 Table 17 P...

Page 267: ...FF C014 bit description 76 Table 73 Fast GPIO port 0 Pin value byte and half word accessible register description 76 Table 74 GPIO port 0 output Set register IO0SET address 0xE002 8004 bit description 77 Table 75 Fast GPIO port 0 output Set register FIO0SET address 0x3FFF C018 bit description 77 Table 76 Fast GPIO port 0 output Set byte and half word accessible register description 77 Table 77 GPI...

Page 268: ...ress 0xE001 C000 and I2C1 I2C1CONSET address 0xE005 C000 bit description 128 Table 122 I2C Control Set register I2CONCLR I2C0 I2C0CONCLR address 0xE001 C018 and I2C1 I2C1CONCLR address 0xE005 C018 bit description 130 Table 123 I2C Status register I2STAT I2C0 I2C0STAT address 0xE001 C004 and I2C1 I2C1STAT address 0xE005 C004 bit description 130 Table 124 I2C Data register I2DAT I2C0 I2C0DAT address...

Page 269: ...xternal Match Register EMR TIMER0 T0EMR address 0xE000 403C and TIMER1 T1EMR address0xE000 803C bit description 195 Table 172 External match control 196 Table 173 PWM Control Register PWMCON TIMER0 PWM0CON 0xE000 4074 and TIMER1 PWM1CON 0xE000 8074 bit description 196 Table 174 Timer Counter pin description 201 Table 175 TIMER COUNTER2 and TIMER CT3OUNTER3 register map 202 Table 176 Interrupt Regi...

Page 270: ...d 244 Table 228 IAP Copy RAM to flash command 245 Table 229 IAP Erase sector s command 246 Table 230 IAP Blank check sector s command 246 Table 231 IAP Read Part Identification command 246 Table 232 IAP Read Boot code version number command 247 Table 233 IAP Compare command 247 Table 234 Reinvoke ISP 247 Table 235 IAP status codes summary 248 Table 236 EmbeddedICE pin description 250 Table 237 Emb...

Page 271: ... transfer 173 Fig 47 Microwire frame format continuos transfers 174 Fig 48 Microwire frame format continuos transfers details 174 Fig 49 Sample PWM waveforms with a PWM cycle length of 100 selected by MR3 and MAT3 0 enabled as PWM outputs by the PWCON register 197 Fig 50 A timer cycle in which PR 2 MRx 6 and both interrupt and reset on match are enabled 198 Fig 51 A timer cycle in which PR 2 MRx 6...

Page 272: ...0xE01F C148 21 3 5 5 External Interrupt Polarity register EXTPOLAR 0xE01F C14C 21 3 6 Other system controls 22 3 6 1 System Control and Status flags register SCS 0xE01F C1A0 23 3 7 Memory mapping control 23 3 7 1 Memory Mapping control register MEMMAP 0xE01F C040 23 3 7 2 Memory mapping control usage notes 23 3 8 Phase Locked Loop PLL 24 3 8 1 Register description 24 3 8 2 PLL Control register PLL...

Page 273: ... 4 9 Vector Control registers 0 15 VICVectCntl0 15 0xFFFF F200 23C 51 5 4 10 Vector Address registers 0 15 VICVectAddr0 15 0xFFFF F100 13C 52 5 4 11 Default Vector Address register VICDefVectAddr 0xFFFF F034 52 5 4 12 Vector Address register VICVectAddr 0xFFFF F030 52 5 4 13 Protection Enable register VICProtection 0xFFFF F020 52 5 5 Interrupt sources 53 5 6 Spurious interrupts 55 5 6 1 Details an...

Page 274: ... U0IER 0xE000 C004 when DLAB 0 87 9 3 7 UART0 Interrupt Identification Register U0IIR 0xE000 C008 Read Only 88 9 3 8 UART0 FIFO Control Register U0FCR 0xE000 C008 90 9 3 9 UART0 Line Control Register U0LCR 0xE000 C00C 90 9 3 10 UART0 Line Status Register U0LSR 0xE000 C014 Read Only 91 9 3 11 UART0 Scratch Pad Register U0SCR 0xE000 C01C 92 9 3 12 UART0 Auto baud Control Register U0ACR 0xE000 C020 9...

Page 275: ...ADR address 0xE005 C00C 131 11 7 6 I2C SCL HIGH duty cycle register I2SCLH I2C0 I2C0SCLH 0xE001 C010 and I2C1 I2C1SCLH 0xE0015 C010 131 11 7 7 I2C SCL Low duty cycle register I2SCLL I2C0 I2C0SCLL 0xE001 C014 I2C1 I2C1SCLL 0xE0015 C014 131 11 7 8 Selecting the appropriate I2C data rate and duty cycle 131 11 8 Details of I2C operating modes 132 11 8 1 Master Transmitter mode 133 11 8 2 Master Receiv...

Page 276: ...NT 0xE002 001C 164 12 5 Architecture 164 Chapter 13 SSP Controller SPI1 13 1 Features 166 13 2 Description 166 13 3 Bus description 167 13 3 1 Texas Instruments Synchronous Serial SSI frame format 167 13 3 2 SPI frame format 168 13 3 3 Clock Polarity CPOL and Clock Phase CPHA control 168 13 3 4 SPI format with CPOL 0 CPHA 0 169 13 3 5 SPI format with CPOL 0 CPHA 1 170 13 3 6 SPI format with CPOL 1...

Page 277: ...8 Match Control Register MCR TIMER0 T0MCR 0xE000 4014 and TIMER1 T1MCR 0xE000 8014 193 15 5 9 Capture Registers CR0 CR3 194 15 5 10 Capture Control Register CCR TIMER0 T0CCR 0xE000 4028 and TIMER1 T1CCR 0xE000 8028 194 15 5 11 External Match Register EMR TIMER0 T0EMR 0xE000 403C and TIMER1 T1EMR 0xE000 803C 195 15 5 12 PWM Control Register PWMCON TIMER0 PWM0CON 0xE000 4074 and TIMER1 PWM1CON 0xE00...

Page 278: ...14 Alarm register group 219 17 5 RTC usage notes 220 17 6 Reference clock divider prescaler 220 17 6 1 Prescaler Integer register PREINT 0xE002 4080 221 17 6 2 Prescaler Fraction register PREFRAC 0xE002 4084 221 17 6 3 Example of prescaler usage 221 17 6 4 Prescaler operation 222 17 7 RTC external 32 kHz oscillator component selection 223 Chapter 18 WatchDog Timer WDT 18 1 Features 225 18 2 Applic...

Page 279: ...code version number 241 19 8 13 Compare address1 address2 no of bytes 241 19 8 14 ISP Return codes 241 19 9 IAP commands 242 19 9 1 Prepare sector s for write operation 244 19 9 2 Copy RAM to flash 245 19 9 3 Erase sector s 246 19 9 4 Blank check sector s 246 19 9 5 Read part identification number 246 19 9 6 Read boot code version number 247 19 9 7 Compare address1 address2 no of bytes 247 19 9 8 ...

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