Circuit Diagrams and PWB Layouts
57
LC7.5E LA
7.
SSB: FPGA I/O Banks
VCCA_PLL
VCCD_PLL
GNDA_PLL
GND
GND
GND
VCCIO4
VCCINT
1
2
1
2
2
1
GND_PLL2
GND_PLL1
VCCIO3
VCCIO2
VCCIO1
NC
NC
CLK
MSEL
6
5
4
3
2
1
0
7
DATA0
DCLK
TDI
TDO
TMS
TCK
1
0
CONF_DONE
CONFIG
STATUS
CE
FPGA I/O BANKS
NC
NC
NC
NC
NC
NC
RES
NC
NC
FROM TRIDENT
FROM TRIDENT
INPUT BANK
TO LVDS
OUTPUT BANK
TO LVDS
FPGA BYPASS
RES
RES
5701 B1
5702 C1
5703 D1
5704 E1
5705 E2
7700-1 F8
7700-2 G3
7700-3 B14
7700-4 H13
7700-5 B8
7700-6 E14
7700-7 I15
F701 B2
F702 B2
F703 C2
F704 E2
F705 E2
F706 F9
F733 G9
F734 F9
I705 G4
I712 G4
I713 H2
I728 H2
3749 B6
3750 F6
3751 F6
3752 G6
3753 G6
4700 F10
4701 G10
4703 C12
4704 C12
4705 C12
4706 C12
4707 C12
4708 C12
4709 C12
4710 C12
4711 C12
4712 C12
4713 D12
4714 D12
4715 D12
4716 D12
4717 D12
4718 D12
4719 D12
4720 D12
4721 D12
4722 D12
4723 C12
4724 D12
4725 D12
4726 E12
5700 B1
3703 F9
3713 G7
3714 F7
3720 B10
3721 B10
3722 B10
3723 B10
3724 B10
3725 C10
3726 C10
3727 C10
3728 C10
3729 C10
3730 D10
3731 D10
3732 E10
3733 E10
3734 E10
3735 C6
3736 C7
3737 C6
3738 B6
3739 B7
3740 B6
3741 C6
3742 C7
3743 C6
3744 D6
3745 D7
3746 D6
3747 B6
3748 B7
J
2700 H1
2701 B2
2702 B3
2703 B4
2704 B4
2705 B4
2706 C2
2707 C2
2708 C2
2709 C3
2710 C3
2711 C3
2712 C4
2713 C4
2714 C4
2715 C4
2717 C2
2718 C2
2719 C2
2720 C3
2721 C3
2724 D2
2725 D3
2726 D3
2729 E2
2730 E3
2734 G8
3700 F10
3701 F10
3702 G11
F734
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
10K
3703
10K
3701
22R
3752
3753
22R
3751
22R
22R
3750
4724
4723
4725
4726
4722
4721
4720
4718
4719
4717
4716
4715
4714
4713
4712
4710
4711
4709
4708
4707
4706
4705
4704
4703
22R
3749
3748
180R
3747
22R
22R
3746
180R
3745
22R
3744
22R
3743
180R
3742
22R
22R
3740
3741
3739
180R
3737
3738
22R
22R
180R
3736
22R
3735
22R
180R
3733
3734
22R
3732
3731
22R
3730
180R
22R
3729
22R
180R
3727
3728
22R
3726
22R
3725
180R
3724
22R
3723
22R
3722
180R
22R
3721
3720
180R
3714
180R
3713
FPGA_BL_DIMMING
FPGA_BL_BOOST
3702
10K
+1V2-PLL
+3V3_FPGA
+3V3_FPGA
+2V5out-FPGA
+2V5in-FPGA
+1V2-FPGA
+3V3_FPGA
2700
1n0
2734
1n0
I705
I712
I713
I728
F733
F706
2726
10n
10n
2725
2730
10n
+1V2-FPGA
10n
2707
+2V5out-FPGA
+1V2_SW
+1V2-PLL
+2V5_SW
F702
F703
+2V5in-FPGA
+3V3_SW
+3V3_FPGA
2721
10n
10n
10n
2720
2719
10n
4u7
2718
30R
2717
5702
30R
5705
5703
30R
30R
5704
2712
2711
10n
10n
10n
2705
2710
2704
10n
10n
10n
2703
2702
10n
2715
10n
10n
2714
2709
10n
10n
2708
F701
F705
F704
10n
2713
5700
30R
1u0
2701
1u0
2729
2706
4u7
5701
30R
2724
47u
4V
3700
10K
4700
F2
H5
G2
G1
4701
H16
H15
J15
J16
J5
L13
F1
H4
J13
K12
M13
EP2C5F256C7N
G5
H2
H1
J2
J1
D1
D2
D7
D9
E13
E15
7700-1
CONTROL
Φ
K6
K7
C15
K8
N3
N4
N6
N7
P6
R6
C16
EP2C5F256C7N
7700-7
B8
F13
F14
F5
G4
H6
J10
J6
K13
Φ
NC
B16
G14
K14
R16
M10
M7
P10
P7
T15
T2
B1
G3
K3
R1
A15
A2
C10
C7
E10
E7
N5
D12
F12
M5
E12
L6
F11
G9
H10
H7
J7
T16
B15
B2
C8
C9
E8
E9
G8
M6
E11
L5
K9
M8
A16
M9
P8
P9
R15
R2
T1
7700-6
A1
H14
H3
H8
H9
J14
J3
J8
J9
IO_T8|LVDS53p
T9
IO_T9|LVDS52p
EP2C5F256C7N
Φ
POWER
IO_T12|LVDS46p
T13
IO_T13|LVDS45p
T14
IO_T14|LVDS44p
T3
IO_T3|LVDS58p
T4
IO_T4|LVDS56p
T5
IO_T5|LVDS55p
T6
IO_T6
T7
IO_T7|LVDS54p
T8
IO_R3|LVDS58n
R4
IO_R4|LVDS56n
R5
IO_R5|LVDS55n
R7
IO_R7|LVDS54n
R8
IO_R8|LVDS53n
R9
IO_R9|LVDS52n
T10
IO_T10|LVDS49n
T11
IO_T11|LVDS51p
T12
IO_P13|LVDS47n
P4
IO_P4|LVDS57n
P5
IO_P5|LVDS57p
R10
IO_R10|LVDS49p
R11
IO_R11|LVDS51n
R12
IO_R12|LVDS46n
R13
IO_R13|LVDS45n
R14
IO_R14|LVDS44n
R3
IO_L9|LVDS50p
M11
IO_M11|LVDS43p
N10
IO_N10|LVDS59n
N11
IO_N11|VREFB4N0
N8
IO_N8|VREFB4N1
N9
IO_N9|LVDS59p
P11
IO_P11
P12
IO_P12|LVDS47p
P13
K10
IO_K10|LVDS48n
K11
IO_K11|LVDS48p
L10
IO_L10|LVDS50n
L11
IO_L11|LVDS43n
L12
IO_L12
L7
IO_L7|LVDS60p
L8
IO_L8|LVDS60n
L9
G7
IO_G7|LVDS11p
7700-5
EP2C5F256C7N
Φ
BANK4
F10
IO_F10|LVDS12n
F6
IO_F6|LVDS13n
F7
IO_F7|LVDS19n
F8
IO_F8|LVDS19p
F9
IO_F9|LVDS12p
G10
IO_G10|LVDS24n
G11
IO_G11|LVDS24p
G6
IO_G6|LVDS11n
C4
IO_C4|LVDS10p
C5
IO_C5|LVDS10n
C6
IO_C6|LVDS17p
D10
IO_D10|LVDS22p
D11
IO_D11|LVDS22n
D6
IO_D6|LVDS17n
D8
IO_D8|VREFB2N1
E6
IO_E6|LVDS13p
B4
IO_B4|LVDS15n
B5
IO_B5|LVDS16n
B6
IO_B6|LVDS18n
B7
IO_B7|LVDS20p
B9
IO_B9|LVDS21p
C11
IO_C11|VREFB2N0
C12
IO_C12|LVDS27p
C13
IO_C13|LVDS27n
A8
IO_A8
A9
IO_A9|LVDS21n
B10
IO_B10|LVDS23n
B11
IO_B11
B12
IO_B12|LVDS25n
IO_B13|LVDS26n
B13
B14
IO_B14|LVDS28n
B3
IO_B3|LVDS14n
A12
IO_A12|LVDS25p
A13
IO_A13|LVDS26p
A14
IO_A14|LVDS28p
A3
IO_A3|LVDS14p
A4
IO_A4|LVDS15p
A5
IO_A5|LVDS16p
A6
IO_A6|LVDS18p
A7
IO_A7|LVDS20n
7700-3
EP2C5F256C7N
Φ
BANK2
A10
IO_A10|LVDS23p
A11
IO_A11
IO_M4|PLL1_OUTn
M4
IO_N1|LVDS1p
N1
IO_N2|LVDS1n
N2
IO_P1|LVDS0p
P1
IO_P2|LVDS0n
P2
IO_P3
P3
IO_K5|LVDS3n
K5
IO_L1|LVDS2p
L1
IO_L2|LVDS2n
L2
IO_L3
L3
IO_L4|PLL1_OUTp
L4
IO_M1
M1
IO_M2
M2
IO_M3
M3
E4
IO_E5|LVDS8n
E5
IO_F3|VREFB1N0
F3
IO_F4|CSO_
F4
IO_J4|VREFB1N1
J4
IO_K1|LVDS4n
K1
IO_K2|LVDS4p
K2
IO_K4|LVDS3p
K4
IO_C2|LVDS9n
IO_C3|ASDO
C3
IO_D3|LVDS6p
D3
IO_D4|LVDS6n
D4
IO_D5|LVDS8p
D5
E1
IO_E1|LVDS5p
E2
IO_E2|LVDS5n
IO_E3|LVDS7p
E3
IO_E4|LVDS7n
Φ
BANK1
EP2C5F256C7N
7700-2
IO_C1|LVDS9p
C1
C2
IO_N13|LVDS41n
N13
IO_N14|LVDS41p
N14
N15
IO_N15|LVDS39n
N16
IO_N16|LVDS39p
P14
IO_P14
P15
IO_P15|LVDS40n
P16
IO_P16|LVDS40p
IO_L14
L14
L15
IO_L15|LVDS37n
L16
IO_L16|LVDS37p
M12
IO_M12|LVDS42p
M14
IO_M14|VREFB3N1
M15
IO_M15|LVDS38n
M16
IO_M16|LVDS38p
N12
IO_N12|LVDS42n
IO_G16|LVDS34n
G16
H11
IO_H11|LVDS32p
H12
IO_H12|LVDS35n
H13
IO_H13|VREFB3N0
J11
IO_J11|LVDS32n
J12
IO_J12|LVDS35p
K15
IO_K15|LVDS36p
IO_K16|LVDS36n
K16
IO_D16|LVDS30p
D16
IO_E14|PLL2_OUTp
E14
IO_E16
E16
F15
IO_F15|LVDS33n
F16
IO_F16|LVDS33p
G12
IO_G12|LVDS31n
G13
IO_G13|LVDS31p
G15
IO_G15|LVDS34p
EP2C5F256C7N
Φ
BANK3
7700-4
C14
IO_C14|LVDS29n
D13
IO_D13|LVDS29p
D14
IO_D14|PLL2_OUTn
IO_D15|LVDS30n
D15
TxLVDSo_4p
TxLVDSo_4n
TxLVDSo_1n
TxLVDSo_CLKp
TxLVDSo_CLKn
TxLVDSo_3p
TxLVDSo_3n
TxLVDSe_4p
TxLVDSe_4n
TxLVDSe_3p
TxLVDSe_3n
TxLVDSo_0p
TxLVDSo_0n
TxLVDSo_1p
TxLVDSe_0p
TxLVDSe_0n
TxLVDSe_1n
TxLVDSe_2p
TxLVDSe_2n
TxLVDSe_4p
TxFPGAe_CLKn
TxLVDSe_CLKn
TxFPGAe_CLKp
TxLVDSe_CLKp
TxFPGAo_CLKn
TxLVDSo_CLKn
TxFPGAo_CLKp
TxLVDSo_CLKp
TxFPGAo_CLKp
TxFPGAo_CLKn
TxFPGAe_CLKp
TxFPGAe_CLKn
TxFPGAe_0p
TxLVDSe_0p
TxLVDSe_1n
TxFPGAe_1n
TxFPGAe_1p
TxLVDSe_1p
TxLVDSe_2n
TxFPGAe_2n
TxFPGAe_2p
TxLVDSe_2p
TxLVDSe_3n
TxFPGAe_3n
TxFPGAe_3p
TxLVDSe_3p
TxLVDSe_4n
TxFPGAe_4n
TxFPGAe_4p
TxFPGAo_0p
TxLVDSo_0p
TxLVDSo_1n
TxFPGAo_1n
TxFPGAo_1p
TxLVDSo_1p
TxLVDSo_2n
TxFPGAo_2n
TxFPGAo_2p
TxLVDSo_2p
TxLVDSo_3n
TxFPGAo_3n
TxFPGAo_3p
TxLVDSo_3p
TxLVDSo_4n
TxFPGAo_4n
TxFPGAo_4p
TxLVDSo_4p
TxFPGAe_0n
TxLVDSe_0n
TxFPGAo_1p
TxFPGAo_1n
TxFPGAo_2p
TxFPGAo_2n
TxFPGAo_4p
TxFPGAo_4n
TxFPGAo_3p
TxFPGAo_3n
TxFPGAo_0n
TxLVDSo_0n
TxFPGAe_2n
TxFPGAe_1p
TxFPGAe_1n
TxFPGAe_0p
TxFPGAe_0n
TxFPGAe_4p
TxFPGAe_4n
TxFPGAo_0p
TxFPGAo_0n
TxLVDSo_2p
TxLVDSo_2n
TxLVDSe_CLKp
TxLVDSe_CLKn
TxFPGAe_3p
TxFPGAe_3n
TxFPGAe_2p
CLK_OSC1
MAIN_SCL
TxLVDSe_1p
TCK_FPGA
DCLK
TMS_FPGA
TDO_FPGA
TDI_FPGA
DATA0
ambi_pwm(5)
ambi_pwm(0)
ambi_pwm(1)
ASDO
ambi_pwm(4)
nCSO
MAIN_SDA
AMBI_SCL
AMBI_SDA
ambi_pwm(3)
ambi_pwm(2)
B05E
B05E
H_17370_014.eps
010804
3139 123 6273.1