96
LC4.9E AB
7.
Circuit Diagrams and PWB Layouts
SSB: Flash / Control
12
CE
WE
14
17
1
8
6
5
4
3
2
1
0
15
0
10
9
8
7
OE
11
1
3
DQ
16
7
512K-1
0
A
S
CL
ADR
0
1
2
S
DA
WC
FLA
S
H / CONTROL
RE
S
TO
S
CALER
RE
S
RE
S
RE
S
TO HDMI
TO
S
CALER
RE
S
RE
S
RE
S
RE
S
RE
S
For
S
oftw
a
re
Development
only - (RE
S
)
&
TO COLUMBU
S
&
1
2
3
4
5
6
7
1
2
3
4
5
6
7
A
B
C
D
E
A
B
C
D
E
1C00 E4
2C00 A
3
2C01 A
3
2C02 E2
2C0
3
E5
3
C00 E2
3
C01 E5
3
C02 E6
3
C0
3
E6
3
C04-1 A6
3
C04-2 A6
3
C04-
3
A6
3
C04-4 A6
3
C05 A6
3
C06-1 B5
3
C06-2 B5
3
C06-
3
B5
3
C06-4 B5
3
C07-1 B5
3
C07-2 B5
3
C07-
3
B5
3
C07-4 B5
3
C0
8
-1 B5
3
C0
8
-2 B5
3
C0
8
-
3
C5
3
C0
8
-4 C5
3
C09-1 C5
3
C09-2 C5
3
C09-
3
C5
3
C09-4 C5
3
C10-1 C5
3
C10-2 C5
3
C10-
3
C5
3
C10-4 C5
3
C11 A6
3
C12 A6
3
C1
3
A6
3
C14 B6
3
C15 B6
3
C16-1 B7
3
C16-2 B7
3
C16-
3
B6
3
C16-4 B6
3
C17 B6
3
C1
8
B7
3
C19 C6
3
C20 C7
3
C21 C7
5C00 A
3
7C00 A2
7C01 E
3
7C02 E5
FC00 A
3
FC01 E2
FC02 E2
FC0
3
E2
FC04 E4
FC05 E6
FC06 C6
FC07 C6
FC0
8
C7
FC09 B7
FC10 B7
TO
S
CALER
3
V2
0V
3
V2
3
V2
3
V2
3
V2
0V
20
21
24
3
2
16
3
1
5
27
26
22
1
3
14
15
17
1
8
19
3
2
3
0
1
10
9
8
7
6
[FLA
S
H]
12
11
2
3
25
4
2
8
29
M29W040B-55K1
7C00
512Kx
8
ROM
3
2
4
10K
3
C17
S
KQR
1C00
1
3
C11
10K
3
C05
+
3
V
3
_IO
3
C12
3
C1
3
3
C14
3
C15
3
C04-4
10K
45
10K
3
C04-
33
6
27
1
8
3
C04-2
10K
10K
3
C04-1
FC06
FC10
FC07
FC0
8
FC05
FC09
FC0
3
FC04
FC01
FC02
FC00
10K
3
C06-4
4
5
+
3
V
3S
W
10K
3
C06-
3
3
6
10K
3
C06-2
2
7
1
8
4
5
10K
3
C06-1
6
3
C07-4
10K
3
C07-
3
10K
3
3
C07-2
10K
2
7
10K
1
8
10K
3
C0
8
-4
4
5
3
C07-1
3
6
2
7
10K
3
C0
8
-
3
1
8
10K
3
C0
8
-2
10K
3
C0
8
-1
2C00
100n
10K
3
C1
8
3
C21
3
C20
45
+
3
V
3
_IO
3
6
3
C16-4
27
3
C16-
3
10K
3
C16-1
1
8
3
C16-2
3
C19
4
5
3
6
10K
3
C10-4
2
7
10K
3
C10-
3
10K
3
C10-2
10K
3
C10-1
1
8
4
5
3
6
3
C09-4
10K
2
7
3
C09-
3
10K
1
8
3
C09-2
10K
3
C09-1
10K
3
C01
10K
5C00
2C01
10
u
16V
+
3
V
3
_IO
3
C02
1K0
100n
2C02
3
C0
3
+
3
V
3S
W
+
3
V
3S
W
100n
2C0
3
3
C00
10K
6
5
8
4
7
7C01
1
2
3
GND
MR
1
S
UB
2
5
VCC
VOUT
4
M24C
3
2-WMN6
(4Kx
8
)
Φ
EEPROM
7C02
P
S
T596J
3
OCMDATA(0:7)
OCMADDR(0:19)
OCMADDR(1
8
)
OCMADDR(4)
OCMADDR(5)
OCMADDR(6)
OCMADDR(7)
OCMADDR(0)
OCMADDR(1)
OCMADDR(2)
OCMADDR(
3
)
OCMADDR(19)
OCMADDR(10)
OCMADDR(11)
OCMADDR(12)
OCMADDR(15)
OCMADDR(16)
OCMADDR(1
8
)
OCMADDR(17)
OCMADDR(14)
OCMADDR(1
3
)
OCMADDR(
8
)
OCMADDR(9)
OCMADDR(16)
OCMADDR(17)
OCMADDR(2)
OCMADDR(
3
)
OCMADDR(4)
OCMADDR(5)
OCMADDR(6)
OCMADDR(7)
OCMADDR(
8
)
OCMADDR(9)
#ROM_C
S
OCMDATA(0)
OCMDATA(1)
OCMDATA(2)
OCMDATA(
3
)
OCMDATA(4)
OCMDATA(5)
OCMDATA(6)
OCMDATA(7)
#OCM_RE
#OCM_WE
S
DA_IO
NVM_WP_
S
CALER
#RE
S
ET
OCMADDR(0)
OCMADDR(1)
OCMADDR(10)
OCMADDR(11)
OCMADDR(12)
OCMADDR(1
3
)
OCMADDR(14)
OCMADDR(15)
S
CL_IO
B11
B11
3
1
3
9 12
3
6141.1
G_15
3
51_011.ep
s
0
8
0906