56
LC4.9E AB
7.
Circuit Diagrams and PWB Layouts
SSB: Audio Delay line (Reserved)
EN
C1
1D
EN
C1
1D
2C1
14
13
11
10
9
8
7
6
5
4
3
2
1
0
2EN
32k-1
0
A
A,1D
12
A
G2
C2
G1
1+
CT=0
CTR8
(CT=255)Z4
2D 3
4
EN3
C2
G1
1+
CT=0
CTR8
(CT=255)Z4
2D 3
4
EN3
AUDIO DELAY LINE (RESER
V
ED)
COUNTER
COUNTER
LATCH
LATCH
2
V
3
2
V
3
5
V
3
5
V
3
2
V
6
2
V
6
2
V
6
2
V
6
2
V
6
2
V
6
2
V
6
5
V
3
2
V
5
2
V
5
2
V
5
2
V
5
2
V
5
2
V
5
2
V
5
2
V
5
2
V
3
5
V
3
2
V
3
5
V
3
5
V
3
2
V
6
2
V
6
2
V
6
2
V
6
2
V
6
2
V
6
2
V
6
2
V
3
0
V
2
5
V
3
2
V
3
2
V
6
2
V
3
5
V
3
2
V
6
RES
*
RES
RES
RES
RES
RES
RES
RES
RES
*
4510 C9
4511 C9
4512 C9
4513 C9
4514 C9
5501 A1
7501 A1
7502 B3
7503 F1
7504 F6
7505 B7
7506 B8
F501 A2
F502 B2
F503 C10
F504 D10
F505 F10
I501 F5
I502 F6
I503 E2
I504 E2
I505 F2
A
B
C
D
E
F
A
B
C
D
E
F
2501 A2
2502 B2
2503 D2
2504 B8
2505 B9
2506 C10
2507 D10
2508 F6
2509 F7
3501 F6
3502 F6
4501 E2
4502 F2
4503 F2
4504 F3
4505 F3
4506 F3
4507 C9
4508 C9
4509 C9
22
28
27
F502
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
I505
8
9
10
I503
I504
20
11
12
13
15
16
17
18
19
14
9
10
24
25
26
1
2
3
4
5
21
23
6
7
8
CY62256LL-70ZC
7502
32kx8
RAM
82p
2508
470p
2507
20
330p
2506
11
1
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
10
12
20
74HC573PW
7505
10
11
1
19
18
17
16
15
14
13
2
3
4
5
6
7
8
9
74HC573PW
7506
F505
4504
4506
I502
I501
F504
4514
F503
4513
4512
4511
4509
4510
4508
4507
+5
V
D
4505
4502
4501
4503
7504
BC847BW
3502
47K
3501
470R
2509
82p
+5
V
D
2505
100n
+5
V
D
+5
V
D
2504
100n
2502
100n
+5
V
D
+5
V
D
2503
100n
100n
2501
+5
V
D
+5
V
D
+5
V
D
F501
5501 1
u
0
6
7
13
9
V
CC
16
+5
V
SWI
GND
8
14
15
1
2
3
4
5
11
12
10
5
6
7
13
9
16
V
CC
7503
M74HC590T
GND
8
14
15
1
2
3
4
7501
M74HC590T
11
12
10
I2SDI1
I2SCLK
I2SDO1
B4
B4
3139 123 6093.1
F_15430_004.eps
140405
4503
4504
LCD PDP
N
Y
Y
N
*
