Circuit Diagrams and PWB Layouts
105
LC4.9E AB
7.
SSB: EPLD
INIT_DONE
CLKU
S
R
4
3
2
1
0
6
5
4
3
2
VCC
RA
RB
RC
RB-
RC+
RC-
RD+
RD-
RCLK+
RCLK-
PDWN
CLKOUT
PLLVCC
RD
GND
LVD
S
GND
PLLGND
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
LVD
S
VCC
RA+
RA-
RB+
S
TATU
S
2
1
0
CEO
TM
S
TCK
TDO
TDI
S
CAN
CLK
M
S
EL
3
A
S
DO
C
S
O
DCLK
DATA0
1
0
CE
CONFIG
CONF_DONE
DATA
GND
A
S
DI
DCLK
C
S
_
VCC
RE
S
RE
S
RE
S
RE
S
RE
S
EPLD
TO
S
CALER
TO
S
CALER
TO EPLD
TO
S
CALER INTERFACE
TO TOP CONN.
FOR DEBUGGING
LVD
S
IN
INTERFACE
FOR NON-
PIXEL+
S
ET
S
RE
S
FOR DEVELOPMENT
U
S
E ONLY
B21
FN24 F11
FN25 G
3
FN26 D1
FN27 D1
FN2
8
D1
FN29 D1
FN
3
0 D1
FN
3
1 D2
FN
3
2 D2
FN
33
D2
FN
3
4 D2
FN
3
5 D2
IN01 B2
IN02 B2
IN0
3
B2
IN04 B2
IN05 B
3
IN06 C2
IN07 E
3
IN0
8
C1
IN09 C1
IN10 B
3
IN11 B
3
IN12 C4
IN1
3
D4
IN14 D4
IN15 D10
IN16 D10
IN17 D10
IN1
8
D10
IN19 F
8
5N05 C5
6N01 F
8
7N01 A2
7N02-1 A4
7N02-2 D6
7N02-5 D9
7N0
3
-1 C2
7N0
3
-2 C1
7N04 D4
FN01 B
3
FN02 B5
FN0
3
C5
FN04 B7
FN05 B7
FN06 B7
FN07 B7
FN0
8
B
8
FN09 B7
FN10 B
8
FN11 E5
FN12 E5
FN1
3
F5
FN14 F5
FN15 F5
FN16 F5
FN17 G5
FN1
8
D
8
FN19 D
8
FN20 F
8
FN21 F10
FN22 F11
FN2
3
F11
3
N42 F10
3
N4
3
F10
3
N44 F10
3
N45 F10
3
N46 D9
3
N47 D9
4N01 D1
4N02 D1
4N0
3
D1
4N04 D1
4N05 D1
4N06 D1
4N07 D1
4N0
8
D1
4N09 D2
4N10 D1
4N11 D2
4N12 D2
4N1
3
D2
4N14 D2
4N15 D2
4N16 D2
4N17 D2
4N1
8
D2
4N19 D2
4N20 D2
4N21 D
8
4N22 D
8
5N01 A7
5N02 D
3
5N0
3
D4
5N04 D4
3
N10 C1
3
N11 C4
3
N12 B4
3
N1
3
B5
3
N14 B5
3
N15 B6
3
N16 B6
3
N17 B6
3
N1
8
B6
3
N19 C5
3
N20 C5
3
N21 E2
3
N22 E2
3
N2
3
F2
3
N24 F2
3
N25 F2
3
N26 D
3
3
N27 D6
3
N2
8
F
8
3
N29 E10
3
N
3
0 E10
3
N
3
1 E10
3
N
3
2 E10
3
N
33
E10
3
N
3
4 E10
3
N
3
5 E10
3
N
3
6 F10
3
N
3
7 F10
3
N
38
F10
3
N
3
9 F10
3
N40 F10
3
N41 F10
1N02 D10
1N0
3
F11
1N05 D5
2N01 A1
2N02 C1
2N0
3
C1
2N04 C2
2N05 D
3
2N06 D
3
2N07 D4
2N0
8
D4
2N09 D4
2N10 D5
2N11 B6
2N12 B6
2N1
3
B6
2N14 B7
2N15 B7
2N16 E10
2N17 G10
2N1
8
G11
2N19 G11
2N20 G11
3
N01 B2
3
N02 B2
3
N0
3
B2
3
N04 B2
3
N05 B
3
3
N06 B
3
3
N07 C1
3
N0
8
C2
3
N09 B
3
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
A
B
C
D
E
F
G
1N01 A
8
FN
3
5
1
2
3
4
5
FN
3
4
FN
3
2
FN
33
FN
3
1
FN29
FN
3
0
FN27
FN2
8
FN26
IN19
IN17
IN1
8
IN16
IN1
3
IN15
IN14
IN11
IN12
IN10
IN0
8
IN09
3
N47
100R
3
N46
100R
4N17
4N19
4N1
3
4N09
4N15
4N07
4N11
4N05
4N01
4N0
3
3
N25
100R
3
N24
3
N2
3
100R
100R
100R
3
N22
3
N21
100R
FN1
8
FN19
100p
2N16
+
3
V
3S
W
3
N45
100R
5
6
100p
2N20
1N02
B4B-PH-
S
M4-TBT(LF)
1
2
3
4
4N22
4N21
100R
3
N40
100R
3
N
3
9
3
N41
100R
100R
100R
3
N
3
6
3
N
3
7
3
N
38
100R
4N20
4N1
8
4N16
4N12
4N14
4N0
8
4N10
4N06
4N04
4N02
100R
3
N
33
100R
3
N
3
4
3
N
3
5
100R
100R
3
N
3
1
3
N
3
0
100R
100R
3
N
3
2
4
5
6
7
1N0
3
BM05B-
S
R
SS
-TBT
1
2
3
2N1
8
100p
100R
2N17
100p
100R
3
N4
3
3
N42
100R
3
N44
2N19
100p
FN2
3
FN24
FN21
FN22
3
N29
FN20
100R
3
N2
8
1
8
0R
3
N27
47R
TLMG
3
100
+
3
V
3
-IO
T15
IO_
88
R15
6N01
M11
IO_
8
0
M12
P12
IO_
8
1
IO_
8
2
R12
IO_
83
T1
3
IO_
8
4
R1
3
IO_
8
5
R14
IO_
8
6
P1
3
IO_
8
7
T11
IO_72
N10
IO_7
3
P10
IO_74
R11
IO_75
P11
IO_76
N11
IO_77
N12
IO_7
8
M9
IO_79
N
8
IO_64
P
8
IO_65
M10
IO_66
R9
IO_67
T9
IO_6
8
P9
IO_69
N9
IO_70
R10
IO_71
M7
IO_56
T6
IO_57
R7
IO_5
8
P7
IO_59
N7
IO_60
R
8
IO_61
T
8
IO_62
M
8
IO_6
3
IO_47
IO_4
8
P5
IO_49
M5
IO_50
M6
IO_51
N5
IO_52
N6
IO_5
3
P6
IO_54
R6
IO_55
IO_41
R2
IO_42
T2
IO_4
3
R
3
IO_44
P4
IO_45
R4
IO_46
T4
R5
IO_9
F5
Φ
BANK 4
EP1C12F256C
8
7N02-5
IO_
3
C2
IO_4
B1
IO_40
N4
IO_5
G5
IO_6
F4
IO_7
D
3
IO_
8
E4
IO_
3
2
L5
IO_
33
M4
IO_
3
4
N
3
IO_
3
5
K5
IO_
3
6
L4
IO_
3
7
R1
IO_
38
P2
IO_
3
9
P
3
IO_25
L1
IO_26
L2
IO_27
M1
IO_2
8
N1
IO_29
M2
IO_
3
0
N2
IO_
3
1
M
3
IO_1
D4
IO_2
C
3
IO_20
H5
IO_21
J1
IO_22
K2
IO_2
3
L
3
IO_24
K1
IO_12
E2
IO_1
3
D1
IO_14
F
3
IO_15
G
3
IO_16
F2
IO_17
E1
IO_1
8
G2
IO_19
F1
Φ
IO_10
E
3
IO_11
D2
IN07
7N02-2
EP1C12F256C
8
BANK 1
5N02
5N04
5N0
3
100n
2N09
FN25
FN11
FN15
FN16
FN17
FN14
FN12
FN1
3
3
N26
4K7
+
3
V
3S
W
+
3
V
3S
W
100n
2N06
+
3
V
3S
W
100n
2N05
2N0
8
100n
100n
2N07
2
3
1
40
4
8
56
1
8
17
20
19
7
3
4
41
42
49
50
47
51
16
15
5
3
54
55
1
3
5
6
33
3
5
3
7
12
11
38
3
9
4
3
45
46
1
3
25
22
24
2
3
10
9
27
29
3
0
3
2
THC6
3
LVDF
8
4B
26
4
2
8
3
6
44
52
8
14
21
+
3
V
3
-IO
RECEIVER
INTERFACE
LCD PANEL
Φ
7N04
3
N11
IN05
47R
IN06
FN01
FN09
IN04
IN02
IN0
3
5N01
IN01
5N05
33
K
3
N07
FN0
3
FN10
FN0
8
FN07
FN06
FN04
FN05
+
3
V
3
-IO
FN02
3
N0
3
10K
3
N02
10K
3
N01
3
N20
10K
+
3
V
3
-IO
47R
2N10
100n
1
4
3
OC
14M
3
1
8
1
8
1N05
2
G4
H2
K4
J
3
J2
J1
3
J14
H14
H15
J15
7N02-1
EP1C12F256C
8
K
3
H4
J4
G1
H1
G16
H16
H
3
K1
3
CONTROL
Φ
2N04
1n0
2
6
1
4
7N0
3
-1
BC
8
47B
S
BC
8
47B
S
7N0
3
-2
5
3
100p
2N15
2N12
47R
3
N1
8
2N11
47R
3
N16
2N14
3
N15
3
N17
47R
47R
2N1
3
+
3
V
3
-IO
2N01 100n
5
1
2
6
4
3
7
8
Φ
S
CD
7N01
EPC
S
4
S
I
8
+
3
V
3
-IO
+
3
V
3
-IO
+
3
V
3
-IO
4
5
6
7
8
9
1N01
1
10
2
3
3
N12
10K
1
u
0
2N0
3
3
N10
33
K
3
N0
8
10K
3
N19
10K
10K
3
N09
1K0
3
N1
3
+
3
V
3
-IO
10K
3
N04
3
N06
10K
10K
3
N14
3
N05
10K
2N02
100n
S
DA_IO
LVD
S
Bp
LVD
S
Bn
LVD
S
Cp
LVD
S
Cn
LVD
S
Dp
LVD
S
Dn
LVD
S
CLKp
LVD
S
CLKn
R_LB_PWM
B_LB_PWM
G_LB_PWM
R_RB_PWM
B_RB_PWM
G_RB_PWM
S
CL_IO
R_LT_PWM
B_LT_PWM
G_LT_PWM
R_RT_PWM
B_RT_PWM
G_RT_PWM
LVD
S
Ap
LVD
S
An
TXB2+
TXB1+
TXB
3
+
DE_IN
B_IN(
3
)
V
S
_IN
B_IN(5)
H
S
_IN
LVD
S
_PWR_DWN
BACKLIGHT_DIM
R_IN(4)
R_IN(7)
R_IN(5)
G_IN(0)
G_IN(1)
G_IN(7)
G_IN(
3
)
B_IN(0)
G_IN(5)
B_IN(4)
B_IN(6)
R_IN(6)
B_IN(1)
B_IN(2)
PARITY_IN
TXBC+
TXB1-
H
S
_IN
PIXEL+_RE
S
ET
LED_OUT
B_IN(7)
G_IN(4)
G_IN(6)
G_IN(2)
R_IN(1)
R_IN(0)
R_IN(2)
R_IN(
3
)
R_IN(0)
R_IN(1)
R_IN(2)
R_IN(
3
)
R_IN(4)
R_IN(7)
R_IN(5)
R_IN(6)
G_IN(0)
G_IN(1)
G_IN(2)
G_IN(6)
G_IN(
3
)
G_IN(4)
G_IN(5)
B_IN(0)
B_IN(6)
B_IN(7)
B_IN(1)
B_IN(2)
B_IN(
3
)
B_IN(4)
B_IN(5)
TXBC-
TXB0-
TXB0+
TXB2-
TXB
3
-
PARITY_IN
G_IN(7)
V
S
_IN
DE_IN
CLK_REF
B20
B20
3
1
3
9 12
3
6141.1
G_15
3
51_020.ep
s
0
8
0906