EN 138
3139 785 32804
8.
IC Internal Block Diagrams
IC7500 – SAA7136AE – MULTISTANDARD AUDIO/VIDEO DECODER
BLOCK DIAGRAM
Fig.2 System Block Diagram of SAA7136
SAICO
S-video
Analog Sound Input
Sound Decoder
Analog
16-bit
Stereo ADC
Front End
NF/Audio
Stereo
BUFFER
Analog
Video
ADC
Front End
Video
10-Bit
AI31
AI32
AI33
SSIF
CVBS
Sound
Audio
Inputs
Port B
TS data
Digital
Inputs
Data
IR in
Digital Video
Decoder
Comb Filter
Video Scaler
Format
DACs
Stereo
I
2
S
Audio
Output
MUX
I
2
S
Audio
Stereo
VIP Host
DSP
I
2
S
SPDIF
Dual FM/NICAM
BTSC
EIAJ
dBx expander
(***)
Volume control
Bass, Treble and
Balance
SRC
Incredible Sound
I
2
S
I
2
S
SPDIF
SPDIF
VIP
Analog
Video
ADC
Front End
Video
10-Bit
AI40P
AI41
AI42
AI43
Analog
Video
ADC
Front End
Video
10-Bit
AI11
AI12
AI13
IF_POS
(*)
Analog
Video
ADC
Front End
Video
10-Bit
AI21
AI22
AI23
NAICO
Analog
Control
Input
Video
Unit
Control Unit
Component
Processing
SDTV/HD
Sync.
VBI Slicer
Digital
Low IF
IF
(*)
H-
Scaler
PRE
V-
Scaler
Task A (Video)
Task B
RAW VBI
Scaler Event Handler
EDDI
D
C
I
O
S
T
P
S
C
A
L
E
R
Dig.
Video
Output
Dig. Video IN
DI_A_x
Scaler PLL
Port D
Port C
Video
DAC
ITU
VMI
VIP
Video
I
2
C Slave
TS/PS In
Remote Control
VIP Host Port with
I
2
C Bus
IR out
Remote Control
Receiver
Transmitter
PHI
PHI Bus
VIP_Host_Audio
VIP_Host_Audio
Initiator
INT_A
IRQ &
Main Control
audio
conversion
TS - Out & Audi - In
Silent
I
2
C Bus
Sound
Audio
Outputs
low IF
SSIF & RGB
(**)
/YP
b
P
r
Video
Inputs
Digital
Programming and Control Ports
M
ADC
X
U
3-Bit
FSW
AV
D-C
FSW
AV/DC
Status bits
A
udio Processing
Video Processing
Prog
ramming and Control
Processing
Programming
AUX Inputs
Port A
Video
Output
Ports
DI_E_x
AI40N
IF_NEG
(*)
I
2
S
Audio
DAC
CVBS
Register Array
I
2
C
read back
PHI
FIFO
Processing
H,V
Soft
Mixer
8-bit/
10-bit
IN1_Left
IN1_Right
IN3_Left
IN3_Right
IN2_Left
IN2_Right
OUT2_Left
OUT2_Right
OUT1_Left
OUT1_Right
DVO_D_X
DVO_C_X
SSIF (*)
CVBS (*)
S_IOUTP
S_IOUTN
V_IOUTP
V_IOUTN
DI_B_x
(DI_A_x)
(DI_B_x)
(*)
only SAA7136E, (**) only SAA7136E/AE/DE,
only SAA7136E/AE/BE
(***)
Figure 8-8
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