EN 117
3139 785 31150
7.
Circuit Diagrams and PWB Layouts
Analog: Digital In / Out (DIGIO)
1
1
1
1
1
1
OPTICAL
CHINCH
F
1925 C9
2700 A4
2701 A4
2702 C5
2703 C7
2705 E8
3700 A4
I703 C5
OUT
1
2
4
5
6
7
8
9
1
C
D
E
DIGITAL
0005 E1
I704 C5
I705 C6
I706 D5
from PS
OUT
DIGITAL
3701 C4
3702 C6
3703 C6
3704 C6
3705 D6
3714 D8
6255 D9
6701 C7
7700-1 C3
7700-2 C4
7700-3 C4
7700-4 D4
7700-5 D4
7700-6 B3
F700 C7
F701 D8
F702 D8
I700 A4
I701 C3
I702 C4
9
8
3
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A
B
7700-4
74HCU04D
I701
I702
I706
n
0
0
1
5
0
7
2
I704
5V
V
5
2
F700
18R
3704
5V
0
0
7
2
n
0
1
BRACKET
0005
F701
I705
10
I703
74HCU04D
7700-5
11
I700
3
0
7
3
5V
74HCU04D
3
4
R
5
7
1
3
2
7700-2
1925
YKC21-3416
4
1
7
3
R
7
4
Digital In/Out DIGIO
2
74HCU04D
7700-1
1
F702
0
0
7
3
R
0
1
6255
JFJ1000
GND
3
IN
1
VS
2
8
V
6
C-
4
8
3
X
Z
B
1
0
7
6
5V
3702
6
100R
74HCU04D
7700-3
5
4n7
2702
4
1
12
1K0
3705
74HCU04D
7700-6
13
7
p
0
9
3
3
0
7
2
120R
3701
DAOUT
V
0
1
0
u
1
1
0
7
2
3139_243_32604_a3_sh130_sh7.pdf 2005-05-18
F700 DIGITAL_OUT
F702 OPTICAL_OUT