Circuit Descriptions, Abbreviation List, and IC Data Sheets
EN 121
EJ2.0U LA
9.
9.5.9
Diagram B6, ADV7123KSTZ140 (IC 7G40)
Figure 9-18 Internal block diagram and pin configuration
G_16290_083.eps
020206
Pin Configuration
Block Diagram
R9–R0
GND
R
SET
IOR
IOR
COMP
ADV7123
V
REF
VOLTAGE
REFERENCE
CIRCUIT
G9–G0
B9–B0
IOG
IOG
IOB
IOB
PSAVE
POWER-DOWN
MODE
BLANK
SYNC
CLOCK
V
AA
DAC
10
DATA
REGISTER
10
DAC
10
DATA
REGISTER
10
DAC
10
DATA
REGISTER
10
BLANK AND
SYNC LOGIC
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
3
R
E
V
A
S
P
8
R
2
R
6
R
5
R
7
R
0
R
1
R
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
V
REF
COMP
IOR
IOR
IOG
IOG
V
AA
4
B
V
A
A
0
B
1
B
2
B
3
B
5
B
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
SYNC
V
AA
IOB
IOB
GND
6
B
7
B
8
B
9
B
R
T
E
S
ADV7123
K
C
O
L
C
BLANK
GND
9
R
4
R