Section 4
FUNCTIONAL
4
DESCRIPTION
page 4.3
RCP–48X
Functional
Reset
As with all microprocessors, the 68HC11 requires initialization during
power-up. The 68HC11 requires that the RESET pin (U1 pin 17) be held
low for 4064 cycles of E clock (2.2 mS @ 1.8432 MHz E clock). In addition
the RESET pin must be held low while VDD is below legal limits to protect
internal EEPROM register contents. A Maxim MAX690 chip (U5) performs
the reset function for the 68HC11. The MAX690 monitors the supply voltage
and asserts RESET (U5 pin 7) whenever VCC falls below 4.5 Vdc. The
RESET signal is guaranteed to be asserted for a minimum of 50 mS after
VCC rises above 4.75 Vdc. This is more than adequate to meet the 2.2 mS
requirement of the 68HC11. The RESET signal is available to external
boards via J2 pin 11.
Memory
The CPU board contains 8K of static RAM (U3). The RAM is selected when
both CS1 (U3 pin 20) and CS2 (U3 pin 26) are asserted. CS1 is low active
and is driven by address bit A15. Whenever A15 is low, CS1 is asserted.
This occurs for addresses in the range of 0000h to 7FFFh. CS2 is high
active and is asserted when address bit A14 is high and E clock is high
(note the AND gate formed by U8 pins 1, 2, and 3 followed by inverter stage
U8 pins 4, 5, and 6). CS2 is active for addresses in the range of 4000h to
7FFFh and C000h to FFFFh. U3 is selected when both CS1 and CS2 are
asserted. This occurs for addresses in the range of 4000h to 7FFFh. This
encloses an address space of 16K. Since U3 is only 8K in length, it is dually
mapped at base addresses of 4000h and 6000h. This means that the same
location in the RAM may be accessed either at 4000h or at 6000h. The
write enable pin WE (U3 pin 27) is driven low during the last half of write
cycles by the U8 pin 8. This WE signal is also availably to external boards
via J1 pin 25.
LED Driver Support
The 68HC11 processor uses the internal synchronous peripheral interface
(SPI) under software control to drive external LED circuitry. LED_DATA is
presented as a serial bitstream on U1 pin 23 and is available to external
boards via J2 pin 7. LED_CLOCK is presented on U1 pin 24 and is avail-
able to external boards via J2 pin 8. External circuitry should accept
LED_DATA on the rising edge of LED_CLOCK. To allow multiple LED
drivers to be serviced, the CPU board provides four select lines labelled
LED_SEL0..LED_SEL3. These low-active signals are presented at U1 pins
30..27 and are available to external boards via J2 pins 1..4. The data
stream generated is compatible with that required by National MM5450 LED
driver chips.
CPU Board Continued:
