FUNCTIONAL
4
DESCRIPTION
Section 4
page 4.2
Functional
RCP–48X
CPU Board Continued:
Microprocessor Continued:
During the first half of the bus cycle, port C presents the lower address
byte (A0-A7). This information is latched into U2 on the falling edge of
address strobe AS (U1 pin 4 to U2 pin 11) and remains stable until the
beginning of the next bus cycle when AS is driven high by the processor.
During the last half of the bus cycle port C presents data during write
cycles and accepts data from an external device during read cycles.
The address bus (A0..A15), the data bus (D0..D7), AS, R/W, and E clock
are available to external boards via J1.
Clock
The master system clock is provided by oscillator U6 pin 8. SYSCLK is
available to the processor (U1 pin 7) and to external boards via J2 pin 10.
The frequency of SYSCLK is 7.3728 MHz. This value was chosen to
provide an appropriate frequency for the baud rate generator inside the
68HC11. The 68HC11 internally divides SYSCLK by four to derive the bus
operating frequency. U1 pin 5 is the E clock used to synchronize all exter-
nal bus cycles. The frequency of the E clock is 1.8432 MHz (SYSCLK/4).
The E clock is used to derive control signals on the CPU board and is
available to external boards via J1 pin 28.
Figure 4–1 Idealized Bus Cycle Timing Diagram
