Copyright © Parallax Inc.
Digital I/O Board Kit (#27113)
v1.0 2/19/2010 Page 10 of 13
Connecting and Testing (Serial Interface)
The serial interface (2x5 header) allows you to reduce the number of pins required to control the Digital
I/O Board by serially shifting data to/from the board over a synchronous serial interface. Whereas full
control requires 16 I/O pins using the parallel interface, the serial interface can provide full control with
as few as 4 I/O pins.
The pins labeled DATA_RLY, SCLK_RLY, LAT_RLY and /OE_RLY are connected to a 74HC595 serial to
parallel shift register. These pins have the following functions: DATA_RLY is serial data going out to the
shift register. This data is sent MSB first (8 bits) synchronously with the SCLK_RLY pin. On the BASIC
Stamp this can be achieved with the SHIFTOUT command. Once the data has been shifted out the
LAT_RLY pin must be pulsed to latch the data onto the outputs. /OE_RLY must be LOW in order for the
74HC595 to drive the relays. This can be tied to VSS or controlled via an I/O pin.
The pins labeled DIN, SCLK_IN and LOAD_IN are connected to a 74HC165 parallel to serial shift register.
These pins have the following functions: DIN is serial data from the shift register sent synchronously with
a clock pulse on SCLK_IN generated by the host microcontroller. On the BASIC Stamp this is achieved
with the SHIFTIN command. Before data is shifted in the current contents of the inputs must be loaded.
This is accomplished by pulsing the LOAD_IN line from HIGH to LOW and then back to HIGH. This line
must remain HIGH during shift operations and must only go LOW during a LOAD operation.
The DIN line has a 1K resistor in series to allow sharing of the 74HC165 data line with the 74HC595
DATA_RLY line. By connecting these lines together and also connecting SCLK_RLY to SCLK_IN you can
reduce the number of I/O pins required by your microcontroller down to four (4). In this configuration
LAT_RLY and LOAD_IN must have their own I/O pins and /OE_RLY can be connected to VSS. This circuit
provides a half-duplex system where you can access one shift register at a time. For full duplex
operation the DIN and DATA_RLY lines must be separate and for independent operation the SCLK_RLY
and SCLK_IN must also be separate.
Note: Do not use the parallel and serial circuits at the same time. Use only one type of interface.
Communication Protocol
The serial protocol (synchronous serial) used by the 74HC595 and 74HC165 is defined in more detail in
the datasheets for each device. BASIC Stamp users can also download the free PDF and example code
for the Stamp Works kit and review experiments 23 through 25 which deal with these shift registers both
independently and together.
Mode Jumper (JP1)
The 3-pin jumper just below the 74HC165 determines whether the data shifted in from the shift register
is inverted or not. Because the optocouplers inherently invert the data, when reading inactive inputs you
get all ones instead zeros which isn’t very intuitive. This jumper allows you to invert the data to
normalize the output and make it more intuitive. In the 1-2 position data is inverted and when an input
is active is will make its output go HIGH. With JP1 in the 2-3 position data is not inverted and when an
input is active you will get a LOW.
Note: The Parallel interface is unaffected by this jumper. Therefore the parallel signals from the
74HC165 are always inverted
