Panasonic PV-DV102PN, Service Manual

Page: 127 / 337

3
VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
REC VIDEO SIGNAL PB VIDEO SIGNAL REC AUDIO SIGNAL PB AUDIO SIGNAL
MAIN C.B.A. CYLINDER UNIT
14
15
17
18
DATA (4 BIT)
DBR (0-3)
IC3201 (FORMATTING/EQUALIZER)
IC3202 (IEEE1394 INTERFACE)
B2
13
FP5
5
FP5
3
FP5
4
FP5
2
REAR C.B.A.
8
27
26
31
30
33
28
29
32
GCA DRIVE
CH1
HEAD
AMP
CH2
HEAD
AMP
IEEE1394
INTERFACE
MICROCONTROLLER
INTERFACE
AGC
DET
(FROM SAFETY TAB SW)
S-TAB ON(L)
LOGIC
MODULATOR
/DEMODULATOR
14
15
16
17
18
19
AMP AMP
LPF
LOGIC
IC5001 (HEAD AMP)
CH 1
HEAD
CH 2
HEAD
ENVELOPE
B2
11
ATF
B2
14
HEAD SW
PULSE
TO INTERFACE BOARD
(FOR EVR ADJUSTMENT)
FROM SYSTEM
CONTROL
BLOCK DIAGRAM
TO/FROM VIDEO I
SIGNAL PROCESS
BLOCK DIAGRAM
JK7003
DV JACK
75
76
79
81
43 1
11
AGC
AMP
6
35
39
41
80
83
B1
14
B1
15
B1
27
B1
26
B1201
14
B1201
15
B1201
27
B1201
26
1
5
2
3
4
TPB(-)
RESET(L) XWEH XWEL
XWEL
XRE
XRE
ADDRESS
STROBE
ADDRESS STROBE
27MHz
CLOCK
27MHz CLOCK
24.576MHz CLOCK
TPB(+)
TPA(-)
TPA(+)
GND
50
51
53
56
58
61
63
66
68
69
41
10 45
27
8
5
3
AMP A/D CONVERTER
AMP A/D CONVERTER
REC-C CONTROL
REC CLOCK
EQ HOLD
REC CONTROL
HEAD SW PULSE 2
HEAD SW PULSE 1
PB(H)
REC ON/OFF CONTROL
D/A CONVERTER
EQUALIZER
ATF DET BPF
AGC CONTROL
VITERBI
43
29
44
38
36
42
39
MICROCONTROLLER
INTERFACE
27MHz CLOCK
(FROM IC6001(71))
RESET(L)
(FROM IC6001(63))
XWEH
(FROM IC6001(64))
XWEL
(FROM IC6001(62))
XRE
(FROM IC6001(61))
ADDRESS STROBE
24.576MHz CLOCK
ADM (0-15)
DBP (0-3)
4
RESET(L)
30 78 77 74 75 88
28
94
74
71
73
20
TO/FROM VIDEO I
SIGNAL PROCESS
BLOCK DIAGRAM
52 54 55 57 58 61 64
66 68 70 73
(TO IC6001(86))
HEAD SW
PULSE 1
TO SYSTEM
CONTROL
BLOCK DIAGRAM
0.1V 5µs 2V 2ms
V1 4Vp-p V1 0.2Vp-p
VIDEO SIGNAL PROCESS II BLOCK DIAGRAM
PV-DV102/PV-DV202/PV-DV402