2-28
2.1.7
VGA circuit (Refer to the page 4-4.)
The SM710 is used as a display controller for this system.
The SM710 is a controller designed in accordance with the SVGA (Super-VGA) Specification that enables color LCD display and
CRT display of 640
×
480 and 800
×
600 dots.
The color TFT is an interface of 18 bits (6 bits
×
3), while the color DSTN is an interface of 16 bits (8 bits
×
2). The image
thickness is controlled by the volume control.
A memory for Video with a capacity of 4Mbytes is incorporated. The interface toward the CPU is connected according to the PCI
bus specification. The signal level is maintained at the TTL level. The basic clock for V-RAM access and display is produced by
the internal PLL of the LSI, based on the 14.318MHz (14MHz) clock.
The SM710 executes initialize setting of the hardware by using the data bus (VMD0~22) of the Video-RAM when the reset
condition is canceled.
There are the operational functions that can be set again by software and those available only by hardware setting.
Signal
1
0
Description
MD 0
7 MCLK
8 MCLK
External Memory Refresh to Command Delay
MD 1
3 MCLK
4 MCLK
External Memory RAS to CAS Delay(SGRAM)
MD 2
Reserve
Reserve
Reserve
MD 3
3 MCLK
4 MCLK
External Memory Pre-charge Time (SGRAM)
MD 5
MD 4
MD 4
MD 5
1
1
0
0
1
X
8-bit column address
9-bit column address
10-bit column address
External Memory Column Address Control
MD 6
Reserve
Reserve
Reserve
MD 7
Reserve
Reserve
Reserve
MD 8
Color STN
Color TFT
Color LCD Type
MD 9
Inverted
Normal
TFT FPCLK Select
MD 11
MD 10
MD 10
MD 11
1
1
0
0
1
0
1
0
1280 x 1024
1024 x 768
800 x 600
640 x 480
LCD Display Size
MD 14
MD 13
MD 12
MD 12
MD 13
MD 14
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
9-bit .3bit/R.G.B.
12-bit 4bit/R.G.B.
18-bit 6bit/R.G.B.
24-bit 8bit/R.G.B.
24-bit 12+12bit
Analog
36-bit 18+18bit
Reserve
Color TFT Interface Type
MD 15
24-bit interface
16-bit interface
DSTN Interface Type
MD 16
Reserve (GPR70.0 )
Reserve
User configration Bits
MD 17
Reserve (GPR70.1 )
Reserve
User configration Bits
MD 18
Reserve (GPR70.2 )
Reserve
User configration Bits
MD 19
Reserve (GPR70.3 )
Reserve
User configration Bits
Summary of Contents for JS-170FR Series
Page 2: ......
Page 10: ......
Page 30: ...1 20 ...
Page 80: ...2 50 ...
Page 101: ...3 17 LCD DISPLAY TEST 6 Video Test ENTER 1 OK or 2 NG ...
Page 134: ...4 JS 170FR PCB s 4 1 Main PCB 4 1 1 Main PCB Schematic Diagram 1 10 4 1 ...
Page 135: ...4 1 1 Main PCB Schematic Diagram 2 10 4 2 ...
Page 136: ...4 1 1 Main PCB Schematic Diagram 3 10 4 3 ...
Page 137: ...4 1 1 Main PCB Schematic Diagram 4 10 4 4 ...
Page 138: ...4 1 1 Main PCB Schematic Diagram 5 10 4 5 ...
Page 139: ...4 1 1 Main PCB Schematic Diagram 6 10 4 6 ...
Page 140: ...4 1 1 Main PCB Schematic Diagram 7 10 4 7 ...
Page 141: ...4 1 1 Main PCB Schematic Diagram 8 10 4 8 ...
Page 142: ...4 1 1 Main PCB Schematic Diagram 9 10 4 9 ...
Page 143: ...4 1 1 Main PCB Schematic Diagram 10 10 4 10 ...
Page 144: ...4 1 2 Main PCB Parts Location 4 11 ...
Page 145: ...4 2 MB PCB 4 2 1 MB PCB Schematic Diagram 4 17 ...
Page 146: ...4 18 4 2 2 MB PCB Parts Location ...
Page 148: ...4 3 Peripheral PCB 4 3 1 Peripheral PCB Schematic Diagram 4 20 ...
Page 149: ...4 21 4 3 2 Peripheral PCB Parts Location ...
Page 152: ...5 2 Main PCB 75 Peripherals ...
Page 153: ...5 3 Power Supply Peripherals ...
Page 154: ...5 4 Customer Display Peripherals ...
Page 155: ...5 5 LCD Peripherals ...
Page 156: ...5 6 Inverter PCB Peripherals ...
Page 161: ...Printed in Japan ...