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5.2.2. Digital Baseband Processor
GSM Processor U101
Package 204-Ball CSPBGA
Feature
Complete single chip GSM Programmable Digital Baseband Processor divided into three main subsystems:
1. Control processor subsystem including
■
32-Bit MCU ARM7TDMI control processor
■
58.5 MHz operation at 1.8 V
■
1MB on-chip System SRAM Memory
2. DSP subsystem including
■
16-Bit Fixed Point DSP Processor
■
91 MIPS at 1.7 V
■
16K-word Data and 16K-word Program SRAM
■
4K-word Program Instruction Cache
■
Architecture supports Full Rate, Enhanced Full Rate, Half Rate, and AMR Speech Encoding / Decoding
Algorithms
3. Peripheral Subsystem including
■
Shared Peripheral Bus and Interface Peripherals
Figure 5.6. U101 Functional Block Diagram
UNIVERSAL
SYSTEM CONN.
INTERFACE
SPI
INTERFACE
CHANNEL
CODEC
SIM
INTERFACE
USB
INTERFACE
(U101 only)
VOICEBAND /
BASEBAND
CODEC
INTERFACE
DISPLAY
INTERFACE
ACCESSORY
INTERFACE
KEYPAD /
BACKLIGHT
INTERFACE
MCU
CONTROL
PROCESSOR
SYSTEM
SRAM
DATA
INTERFACE
MEMORY
INTERFACE
SPEECH
CODEC
CHANNEL
EQUALISER
DSP
TEST
INTERFACE
RADIO
INTERFACE