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The transceiver uses a direct conversion receiver which eliminates the requirement for Intermediate Frequency (IF) stages.
The transceiver chip includes three LNAs for each band, a quadrature demodulator, baseband amplifier circuit with I/Q outputs
and three stages of DC-offset correction.
The DCOC correction loop ensures DC-offsets, generated in the U1201, do not overload baseband chain.
The receiver can be calibrated to optimise IP2 performance, which ensures limited baseband interfering signal amplitude.
The U1201 also features an integrated, fully programmable, sigma-delta fraction-N synthesiser suitable for GPRS multi-slot
operation.
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Transceiver - - Receiver
RX LO
source from chip
Figure 5.4. Receiver block diagram
Antenna
RF SAW
FILTER
RXIN
RXIP
RXQN
RXQP
900
1800
1900
T/R
Switch
&
Diplexer
DCOC
LNA
VGA