Orban OPTIMOD-FM 8600, Operating Manual

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TECHNICAL DATA ORBAN MODEL 8600
Component-Level Description:
We will describe composite output #1. IC300 is a high-speed D/A converter
chip that receives the digital composite signal at a 512 kHz sample rate. It
drives buffer amplifier IC308A. IC308A drives a fifth-order passive LC recon-
struction filter C336-C339, L300-L301, R301-303. (This filter is equalized and
phase-corrected in DSP to obtain excellent flatness and phase-linearity. This
achieves high stereo separation.)
IC302A buffers the output of the anti-imaging filter. IC302B is a servo amplifi-
er to remove DC offset at the output of IC302A. IC401B accepts the SCA inputs,
summing them with the composite stereo output of IC302A. Any contribution
from the SCA inputs is therefore are not indicated on the
C
OMPOSITE
L
EVEL
meter displayed by the 8600, because this meter indicates only the composite
signal generated by the DSP.
Digitally controlled attenuator IC402B receives the output of IC401B and sets
the composite output level. IC3B and IC1, a composite high-current buffer am-
plifier, receives the output of IC402B and drives the composite output con-
nector J4B through an RFI attenuator network and optional 75
Ω
build-out re-
sistor R411.
The pilot reference D/A converter IC400 receives serial data from the DSP cir-
cuitry. After being buffered and low-pass filtered by IC401A, the resulting 19
kHz sine wave signal can be connected to J5A through jumper J400.
The composite line driver amplifiers are socketed for easy field replacement;
all other components are surface-mounted and are not field-replaceable.
DSP Circuit
The DSP circuit consists of nine Freescale (formerly Motorola) 250 MHz DSPB56724
dual-core 24-bit fixed-point DSP chips that execute DSP software code to implement
digital signal processing algorithms. Sufficient external memory is installed to im-
plement a diversity delay at 64 kHz sample rate. The MX peak limiter also uses the
external memory for various purposes.
The algorithms filter, compress, and limit the audio signal. The nine DSP chips, each
operating at approximately 500 million instructions per second (MIPS), for a total of
4500 MIPS, provide the necessary signal processing. A sampling rate of 64 kHz and
power-of-two multiples thereof, up to 512 kHz, is used.
System initialization normally occurs when power is first applied to the 8600 and can
occur abnormally if the 8600’s watchdog timer forces the SC520 to reboot. Upon ini-
tialization, the SC520 CPU downloads the DSP executable code stored in the flash
memory. The time between application of power and completion of DSP code down-
load is approximately 7 seconds. Once a DSP chip begins executing its program, exe-
cution is continuous. The SC520 provides the DSP program with parameter data
(representing information like the settings of various processing controls), and ex-
tracts the front panel metering data from the DSP chips.
During system initialization, the SC520 queries the DSP hardware about its opera-
tional status and will display an error message on-screen if the DSP fails to initialize