![background image](http://html.mh-extra.com/html/onkyo/pr-sc885/pr-sc885_service-manual_1636842095.webp)
TERMINAL DESCRIPTION (3/3)
IC BLOCK DI A
GRAMS AND TERMINAL DESCRIPTIONS -54
Q8800: ADV7401 (Multi-Format SDTV/HDTV Video Decoder)
DTC-9.8
Pin No.
Mnemonic
Type
Function
15 SFL/SYNC_ O
UT
O
SFL (Subcarrier Frequency Lock); this pin contains a serial
output stream which can be used to lock the subcarrier
frequency when this decoder is connected to any Analog
Devices digital video encoder. SYNC_OUT is the sl iced sync
output signal only available in CP mode.
64
REFOUT
O
Internal voltage reference output.
65
CML
O
The CML pin is a common-mode level for the internal ADCs.
61, 62
CAPY1–
CAPY2
I
ADC capacitor network.
68, 69
CAPC1–
CAPC2
I
ADC capacitor network.
67
BIAS
O
BIAS is an external bias setting pin. Connect the
recommended resistor (1.35k ) between pin and ground.
86
HS_IN/CS_IN
I
Can be configured in CP mode to be either a digital HS input
signal or a digital CS input signal used to extract timing in a
5-wire or 4-wire RGB mode.
85
VS_IN
I
VS input signal used in CP mode for 5-wire timing mode.
79
DE_IN
I
DE_IN is a data enable input signal used in 24-bit digital
input port mode, for example,
24-bit RGB data from a DVI Rx IC.
35
DCLK_IN
I
DCLK_IN is a clock input signal used in 24-bit digital input
mode (e.g. 24-bit RGB data from a DVI Rx IC) and also in
digital CVBS input mode.
52
SOG
I
SOG is a sync on green input used in embedded sync mode.
77
SOY
I
SOY is a sync on luma input used in embedded sync mode.
www. xiaoyu163. com
QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299