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26
P6
27
P5
28
P4
29
P26
30
P25
31
P24
32
P23
33
P22
34
P21
35
DCLK_
IN
36
LLC1
37
XT
A
L
1
38
XT
A
L
39
DV
D
D
2
3
4
7
6
5
1
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
74
73
72
69
70
71
75
68
67
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
65
40
DGND
41
P3
42
P2
43
P1
44
P0
45
P20
46
ELPF
47
PVDD
48
PVDD
49
AG
N
D
50
AG
N
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
ADV7401
LQFP
TOP VIEW
P11
P32
P31
INT
CS/HS
DGND
DVDDIO
P15
P14
P13
P12
DGND
DVDD
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P10
P9
P8
P27
P7
AIN2
AIN8
AIN1
AIN7
SOG
AIN9
AIN3
TEST1
AGND
CAPY1
CAPY2
AVDD
REFOUT
CML
AGND
BIAS
CAPC1
CAPC2
TEST0
AIN10
AIN4
AIN11
AIN5
AIN12
FB
F
IE
L
D
/D
E
D
E
_
IN
S
O
Y
A
IN
6
A
L
S
B
S
D
A
S
C
L
K
1
P
4
0
P
3
9
V
S
_
IN
H
S
_
IN
P
3
8
P
3
7
D
G
N
D
D
V
D
D
P
1
9
P
1
7
P
1
6
P
3
6
P
3
5
P
3
4
V
S
P
3
3
P
1
8
R
E
S
E
T
Pin No.
Mnemonic
Type
Function
Digital
ground
Analog
ground
P
Digital I/O supply voltage (3.3 V).
P
Digital core supply voltage (1.8 V).
P
Analog supply voltage (3.3 V).
P
PLL supply voltage (1.8 V).
I
FB is a fast switch overlay input that switches between CVBS
and RGB analog signals.
54, 56, 58,
72, 74, 76,
53, 55, 57,
71, 73, 75
AIN1–AIN12
I
Analog video input channels.
42, 41, 28,
27, 26, 25,
23, 22, 10,
9, 8, 7, 94,
93, 92, 91
P2–P9, P12–
P19
O
Video pixel output port.
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS -52
Q8800: ADV7401 (Multi-Format SDTV/HDTV Video Decoder)
TERMINAL DESCRIPTION(1/3)
PIN CONFIGURATION
DTC-9.8
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9
2
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9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
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TEL 13942296513 QQ 376315150 892498299