ON Semiconductor KAC-12040 Manual Download Page 26

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KAC−12040

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Table 15. REGISTER DEFINITION

(continued)

16 bit

Write Address (Hex)

Default Value

Hex/Dec

SPI State

Description

01D1

CC11h

CONFIG Only

Config1

01D9

0000h

CONFIG or IDLE

Config2

01E1

000Ah

CONFIG or IDLE

Analog/Digital Power Mode

01E9

0000h

CONFIG or IDLE

Dual-Video Repetition

01F1

CONFIG or IDLE

Vertical Blanking

01F9

1938d

CONFIG or IDLE

Fixed Frame Period

0201

1376d

CONFIG or IDLE

Line Length (LL)

0209

0028h

CONFIG or IDLE

ADC Bit Depth

0211

0000h

CONFIG or IDLE

FLO Edge

0219

0000h

CONFIG or IDLE

MSO Edge

0709

0000h

Any

CFA Feedback

0711

0000h

Any

Temperature Sensor FB

0719

0000h

Any

General Feedback

2059

0300h

CONFIG Only

Output Bank Select 1

2099

2877h

CONFIG Only

PLL1 Setting

20A1

0861h

CONFIG Only

PLL2 Setting

2449

0432h

CONFIG Only

Sub-LVDS Enable

2479

10ABh

Any

Column Clamp Threshold A

2481

20C7h

Any

Column Clamp Threshold B

2499

0011h

CONFIG or IDLE

Test Pattern Control 1

24A1

0220h

CONFIG or IDLE

Test Pattern Control 2

24B9

202d

CONFIG Only

Slope 1 Length

24C1

101d

CONFIG Only

Slope 2 Length

24C9

101d

CONFIG Only

Slope 3 Length

24D1

101d

CONFIG Only

Slope 4 Length

24D9

101d

CONFIG Only

Slope 5 Length

24E1

420d

CONFIG Only

Slope 6 Length

24E9

0083g

CONFIG Only

Slope 1/2 Gain

24F1

038Fh

CONFIG Only

Slope 3/4 Gain

24F9

0FBFh

CONFIG Only

Slope 5/6 Gain

2501

1F9Fh

CONFIG Only

Slope 7 Gain

2559

4804h

Any

Defect Avoidance Threshold

2561

0006h

Any

Defect Avoidance Enable

25C1

0003h

CONFIG or IDLE

Encoded Sync Config

25C9

000Ah

CONFIG Only

LVDS Power-Down

2619

000Bh

CONFIG Only

Output Bank Select 2

2D89

0000h

CONFIG Only

FLO/MSO Polarity

4001

4100h

Any

Chip Revision Code

4009

0011h

Any

Chip ID Code MSB

4011

0080h

Any

Chip ID Code LSB

4019

0000h

Any

Set Sensor State

4021

0000h

CONFIG or IDLE

OTP Address

Summary of Contents for KAC-12040

Page 1: ... of Active Pixels 4000 H 3000 V Active Image Size 18 8 mm H 14 1 mm V 23 5 mm Diagonal 4 3 Optical Format Master Clock Input Speed 5 MHz to 50 MHZ Maximum Pixel Clock Speed 160 MHz DDR LVDS 320 Mbps Number of LVDS Outputs 64 Differential Pairs Number of Output Banks 8 4 or 2 Frame Rate 12 Mp 1 70 fps 10 bits 1 75 fps 8 bits Charge Capacity 16 000 electrons Quantum Efficiency KAC 12040 CBA KAC 1204...

Page 2: ...ade KAC 12040 CBA JD BA Bayer RGB Color Filter Pattern Micro PGA Package Sealed Clear Cover Glass with AR Coating Both Sides Standard Grade KAC 12040 CBA Serial Number KAC 12040 CBA JD AE Bayer RGB Color Filter Pattern Micro PGA Package Sealed Clear Cover Glass with AR Coating Both Sides Engineering Grade 1 Engineering Grade samples might not meet final production testing limits especially for cos...

Page 3: ...4D 0 4D 6 6D 0 6D 6 8 88 8 88 Odd Row ADC Analog Gain Black Sun Correction LVDS Bank 3 LVDS Bank 5 LVDS Bank 7 0 0 Clk7 7D 0 7D 6 Clk5 5D 0 5D 6 Clk3 3D 0 3D 6 LVDS Bank 0 LVDS Bank 1 Digital Gain Offset Noise Correction Clk1 1D0 1D6 Clk0 0D0 0D6 Timing Control Sub Sampling Averaging 8 104 8 104 3 5 VA 3 3 VD 2 8 VA 2 0 VD 1 8 VA Chip Clock 2 Pins TRIGGER RESETN CSN SCLK MOSI MISO Serial Periphera...

Page 4: ...11 10 9 8 7 6 5 4 3 2 1 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 The center of the pixel array is aligned to the physical package center 2 The region under the sensor die is clear of pins enabling the use of a heat sink 3 Non symmetric mounting holes provide orientation and mounting precision 4 Non symmetric pins prevent incorrect placement in PCB 5 Letter F indica...

Page 5: ...resistor If left floating and at default polarity then the sensor state will not be affected by this pin i e defaults to not triggered mode if floated 6 All of the DI and DO pins nominally operate at 0 V 2 0 V and are associated with the VDD_DIG power supply Table 5 POWER PIN DESCRIPTION Name Voltage Pins Description VDD_LVDS 3 3 V D C04 C05 C23 C24 D04 D24 E04 E24 AA04 AA24 AB04 AB24 AC04 AC05 AC...

Page 6: ...AE06 0DATA6 AD06 0DATA6 Bank 0 LVDS Clock Bank 0 LVDS Data Pin Name Description AC07 2DCLK AC08 2DCLK AE07 2DATA0 AD07 2DATA0 AE08 2DATA1 AD08 2DATA1 AE09 2DATA2 AD09 2DATA2 AE10 2DATA3 AD10 2DATA3 AE11 2DATA4 AD11 2DATA4 AE12 2DATA5 AD12 2DATA5 AE13 2DATA6 AD13 2DATA6 Bank 2 LVDS Clock Bank 2 LVDS Data Pin Name Description AC15 4DCLK AC16 4DCLK AE15 4DATA0 AD15 4DATA0 AE16 4DATA1 AD16 4DATA1 AE17...

Page 7: ... Gain Unity Gain or Referred Back to Unit Gain 1 For monochrome sensor only green LED used Table 8 KAC 12040 ABA CONFIGURATION MONOCHROME Description Symbol Wavelength nm Min Nom Max Unit Sampling Plan Temperature Tested at 5C Test Peak Quantum Efficiency Green NIR1 NIR2 QEMAX 550 850 900 53 15 10 Design 27 Responsivity 84 ke Lux s Design 27 20 Responsivity 7 0 V Lux s Design 27 21 Table 9 KAC 120...

Page 8: ...2 8 Photodiode Dark Current IPD 4 6 70 e p s Die 40 13 9 Storage Node Dark Current IVD 1 200 5 000 e p s Die 40 14 5 Image Lag Lag 1 3 10 Design 27 40 15 Black Sun Anti Blooming XAB 12 10 000 W cm2 xllumSat Design 27 7 14 Parasitic Light Sensitivity PLS 730 Design 27 6 10 Dual Video WDR 140 RS 120 GS dB Design 27 1 11 12 Pulsed Pixel WDR GS Only 100 dB Design 27 12 13 1 RS Rolling Shutter Operatio...

Page 9: ...KAC 12040 www onsemi com 9 TYPICAL PERFORMANCE CURVES Figure 4 Monochrome QE with Microlens Figure 5 Bayer QE with Microlens ...

Page 10: ...rizontal the incident light angle is varied along the wider array dimension For the curves marked Vertical the incident light angle is varied along the shorter array dimension Figure 6 Monochrome Relative Angular QE with Microlens Figure 7 Bayer Relative Angular QE with Microlens ...

Page 11: ...od to use the maximum PLL2 speed 313 320 MHz and control frame rate with minimum Power and maximum image quality is to adjust Vertical Blanking register 01F1h Unnecessary chip operations are suspended during Vertical Blanking conserving significant power consumption and also minimizing the image storage time on the storage node when in Global Shutter Operation Figure 9 Power vs Frame Rate 10 bit M...

Page 12: ...ate vs ADC Bit Depth Increasing the ADC bit depth impacts the frame rate by changing the ADC conversion time The following figure shows the power and Frame rate range for several typical cases Figure 10 ADC Bit Depth Impact on Frame Rate and Power ...

Page 13: ... Cluster Defect A group of 2 to 10 contiguous defective pixels but no more than 3 adjacent defects horizontally 22 3 Column Row Major Defect A group of more than 10 contiguous defective pixels along a single column or row 0 Dark Field Faint Column Row Defect RS 3 dn Threshold GS 10 dn Threshold 0 17 1 Bright Field Faint Column Row Defect RS 12 dn Threshold GS 18 dn Threshold 0 18 1 1 RS Rolling Sh...

Page 14: ...ation 700 dn a 4 frame average image is collected and a 4 frame averaged dark image is subtracted The resultant image is partitioned into 300 sub regions of interest each of which is 200 by 200 pixels in size The average signal level of each sub regions of interest sub ROI is calculated The highest sub ROI average Maximum Signal and the lowest sub ROI average Minimum Signal are then used in the fo...

Page 15: ...e photodiode integration time 7 Black Sun Anti Blooming A typical CMOS image sensor has a light response profile that goes from 0 dn to saturation 1023 dn for KAC 12040 in 10 bit ADC mode and with enough light back to 0 dn The sensor reaching 0 dn at very bright illumination is often called the Black sun artifact and is undesirable Black sun artifact is typically the dominant form of anti blooming...

Page 16: ...mination a 64 average dark image is recorded Dark_ref The el per DN is measured using the photon transfer method Illumination is adjusted blink every other frame such that the mean image output is 70 of the Photodiode Charge Capacity for even frames and with no illumination for odd frames A 64 frame average of Odd Dark Frames is recorded as Dark_Lag Lag Dark_Lag Dark_Ref el per DN Units Electrons ...

Page 17: ...t refer to the Write address All SPI reads are to an even address all SPI writes are to an odd address Sensor States Figure 12 shows the sensor states see the KAC 12040 User Guide for detailed explanation of the States Figure 12 Sensor State Diagram RESETN low or reset Reg 4060h RESET STANDBY CONFIG IDLE RUNNING WAKE UP 50 ms 35µ s 2µ s 2µ s 150µ s RUNNING mode OR TRIGGER pin 50µ s End of acquisit...

Page 18: ...10 bit operation and total 8 66 ms The LVDS time will be dependent on the PLL2 frequency selected If the PLL2 313 MHz then the LVDS data readout will dominate the row time For PLL2 313 MHz the Pixel ADC will set the minimum Line Time The Line Time is not impacted by the selection of Rolling Shutter or Global Shutter mode The KAC 12040 architecture always outputs two rows at once one row from the t...

Page 19: ... Time Configuration Frame A Single Frame of Video Overhead Integration Phase Frame m Integration Phase Frame m 1 Integration Phase Frame m 2 Readout Phase Frame m Readout Phase Frame m 1 Frame Wait Frame Wait 13 80 ms by Default Video Frame Time Readout Wait 8 34 ms by Default 952 Line Times 13 79 ms by Default 1576 Line Times 0 01 ms 1 Line Time If the Integration Phase is less than the Readout P...

Page 20: ... clarity Global Shutter readout mode is selected using Bits 1 0 of Register 01D1h Images can be initiated by setting and holding the TRIGGER input pin or by placing the sensor into RUNNING mode by writing 03d to register 4019h If the TRIGGER input pin is true when at the start of the integration time for the next frame then the sensor will complete an additional frame integration and readout In th...

Page 21: ...t edge is sloped The Figure 18 illustration shows a 2 frame output sequence using the external TRIGGER pin Figure 18 Illustration of Frame Time for Rolling Shutter Readout Integration Time 8 33 ms Integration of Next Frame Overlaps Readout of Previous Frame Frame Readout 13 80 ms Effective Frame Time Video Readout Time Trigger Pin True 2 0 V Time Col Address Axis Row Address Axis Rolling Readout m...

Page 22: ...rogrammed to use 4 or 2 banks however this can result in reduced frame rate and reduction of image quality It is recommended that 8 banks be used when possible Only the 8 bank option is discussed in detail in this specification see the KAC 12040 User Guide for additional detail on 4 and 2 bank mode In order to minimize the LVDS clock rate and power for a given data rate the pixels are output in DD...

Page 23: ...l LVDS clock cycle two rows in parallel for 8 pixels per clock cycle total 5 The pixels are sent out from left to right low column number to high column number So the first 4 pixels are sent out on clock cycle 1 and the next 4 pixels to the right are sent out on clock cycle 2 6 To conserve the number of wires per port the 10 bits per pixel are sent out DDR Dual Data Rate over 5 ports On the fallin...

Page 24: ... D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0 D1 D2 D4 D8 D5 D6 D7 D9 LSB MSB D3 D0...

Page 25: ...me A Integration Lines 0099 0d Any Frame A Definition Frame A Integration Clocks 00A1 10d Any Frame A Definition Frame A Black Level 00A9 001Fh Any Frame A Definition Frame A Gain 00E9 0d Any Frame B Definition Frame B ROI y1 00F1 3016d Any Frame B Definition Frame B ROI h1 00F9 0d Any Frame B Definition Frame B ROI x1 0101 4016d Any Frame B Definition Frame B ROI w1 0109 0d Any Frame B Definition...

Page 26: ...LVDS Enable 2479 10ABh Any Column Clamp Threshold A 2481 20C7h Any Column Clamp Threshold B 2499 0011h CONFIG or IDLE Test Pattern Control 1 24A1 0220h CONFIG or IDLE Test Pattern Control 2 24B9 202d CONFIG Only Slope 1 Length 24C1 101d CONFIG Only Slope 2 Length 24C9 101d CONFIG Only Slope 3 Length 24D1 101d CONFIG Only Slope 4 Length 24D9 101d CONFIG Only Slope 5 Length 24E1 420d CONFIG Only Slo...

Page 27: ...LE These registers can be changed in IDLE or CONFIG states 3 CONFIG Only Sensor must be in CONFIG state to set these registers 4 Only Register 4018h and 4060h may be set when the sensor is in STANDBY state NOTES Decimal hexadecimal binary values 1 b denotes a binary number a series of bits MSB is on the left LSB is on the right 2 h or hex denotes a hexadecimal number Base 16 1 9 A F The letters in...

Page 28: ...will be degraded and may be damaged Operation at these values will reduce Mean Time to Failure MTTF Table 16 SUPPLIES Description Value AVDD_LV VDD_DIG 0 25 V 2 3 V AVDD_HV Vref_P VDD_LVDS 0 25 V 4 V DC Input Voltage at Any Input Pin 0 25 V VDD_DIG 0 25 V Table 17 CMOS INPUTS Parameter Symbol Minimum Typical Maximum Unit Input Voltage Low Level VIL 0 3 0 35 VDD_DIG V Input Voltage High Level VIH 0...

Page 29: ...gurable by SPI Register 01D8h Bit 0 the default is active high i e pin VDD_DIG trigger request Table 19 OPERATING TEMPERATURE Description Symbol Minimum Maximum Unit Operating Temperature Note 1 TOP 40 80 C 1 Under conditions of no condensation on the sensor Table 20 CMOS IN OUT CHARACTERISTICS Parameter Symbol Minimum Typical Maximum Unit Output Voltage Low Level VOL 0 45 V Output Voltage High Le...

Page 30: ... in CONFIG State 330 mW Current in CONFIG State VDD_LVDS AVDD_HV AVDD_LV Vref_P VDD_DIG 0 5 0 5 0 5 0 5 145 mA Power in IDLE State 410 mW Current in IDLE State VDD_LVDS AVDD_HV AVDD_LV Vref_P VDD_DIG 0 5 20 0 5 0 5 145 mA Power in RUNNING State 1 5 W Current in RUNNING State VDD_LVDS in Standard LVDS Mode VDD_LVDS in Sub LVDS Mode AVDD_HV AVDD_LV Vref_P VDD_DIG 164 104 74 12 26 396 mA 1 Voltages r...

Page 31: ...aster MISO O SPI Master Serial Data Input Slave sensor serial data output MOSI I SPI Master Serial Data Output Slave sensor serial data input Table 23 Parameter Minimum Typical Maximum Unit SPI SCK 5 25 50 MHz Duty Cycle on SPI SCK 40 50 60 Clock Polarity and Phase CPOL Clock POLarity and CPHA Clock PHAse are commonly defined in SPI protocol such as to define SCK clock phase and polarity The KAC 1...

Page 32: ...ed during RUNNING state see the Register Summary on page 25 If performing a readback during RUNNING state the delay could be as long as 4 5 ms depending on when in the row the request was sent and the sensor s microcontroller activity at that moment Note that readback does not provide the actual register value being used but reflects the next value to be used All new register writes are placed in ...

Page 33: ...X MSB TCS_SETUP TCYCLE TCS_HOLD THOLD TSETUP TOUT_DELAY TOUT_DELAY_CSN CS SCK MOSI MISO Table 24 SPI TIMING SPECIFICATION Symbol Minimum Value Maximum Value Unit TCYCLE 20 200 ns TSETUP 2 9 ns THOLD 0 8 ns TCS_SETUP 2 5 ns TCS_HOLD 0 1 ns TOUT_DELAY_CSN 3 1 4 7 ns TOUT_DELAY 4 9 8 7 ns ...

Page 34: ...20 20 mV Common Mode Output Voltage VOCM 1 235 1 259 1 275 V VOCM Variation between Complementary Output States DVOCM 25 25 mV High Impedance Leakage Current IOZD 1 1 mA Output Short Circuit Current When D or D Connected to Ground When D or D Connected to 3 3 V IOSD 2 9 12 25 4 3 30 47 mA Output Capacitance CDO 1 3 pF Maximum Transmission Capacitance Load Expected for 260 MHz LVDS Clock 10 pF Tabl...

Page 35: ...Clock Period 4 1563 ps C B A 1563 360 1203 ps If the sampling window is too small the PLL2 can be reduced to increase the window parameter C Alternatively the majority of the transition uncertainty is potential skew between the 7 data lines Using de skewing can remove 350 ps from the uncertainty window Table 29 IN BLOCK LVDS TIMING SPECIFICATION Data Transition Uncertainty Data De Skewing Applied ...

Page 36: ... Sensor Handling and Best Practices Application Note AN52561 D from www onsemi com For information on soldering recommendations please download the Soldering and Mounting Techniques Reference Manual SOLDERRM D from www onsemi com For quality and reliability information please download the Quality Reliability Handbook HBD851 D from www onsemi com For information on device numbering and ordering cod...

Page 37: ... Completed Assembly Figure 27 Completed Assembly 1 of 5 1 See Ordering Information for marking code 2 No materials to interfere with clearance through package holes 3 Imaging Array is centered at the package center 4 Length dimensions in mm units Notes ...

Page 38: ...KAC 12040 www onsemi com 38 Figure 28 Completed Assembly 2 of 5 ...

Page 39: ...KAC 12040 www onsemi com 39 Figure 29 Completed Assembly 3 of 5 ...

Page 40: ...KAC 12040 www onsemi com 40 Figure 30 Completed Assembly 4 of 5 Figure 31 Completed Assembly 5 of 5 ...

Page 41: ...are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized ap...

Page 42: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information ON Semiconductor KAC 12040 ABA JD AA KAC 12040 CBA JD AA KAC 12040 CBA JD BA KAC 12040 ABA JD BA ...

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