KAC−12040
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34
LVDS INTERFACE
The data output can be configured to follow standard
TIA/EIA−644−A LVDS specification or a low power mode
compatible with common Sub-LVDS definition used in
FPGA industry. (Please refer to the KAC−12040 User Guide
for more information).
Unless otherwise noted, min/max characteristics are for
T = −40
°
C to +85
°
C, output termination resistance
RL = 100
W
±
1%, Typical values are at VDD_LVDS =
3.3 V.
Use register 2449h to select standard or Sub-LVDS. This
document assumes that Sub-LVDS is active for all power
measurements. Standard LVDS can increase the average
power consumption as much as 200 mW in the case of
minimum horizontal and vertical blanking.
Table 25. STANDARD LVDS CHARACTERISTICS
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Differential Output Voltage
VOD
250
355
450
mV
VOD Variation between Complementary Output States
D
VOD
−20
−
20
mV
Common Mode Output Voltage
VOCM
1.235
1.259
1.275
V
VOCM Variation between Complementary Output States
D
VOCM
−25
−
25
mV
High Impedance Leakage Current
IOZD
−1
−
1
m
A
Output Short Circuit Current:
When D+ or D− Connected to Ground
When D+ or D− Connected to 3.3 V
IOSD
2.9
12.25
−
−
4.3
30.47
mA
Output Capacitance
CDO
−
1.3
−
pF
Maximum Transmission Capacitance Load Expected
(for 260 MHz LVDS Clock)
−
−
10
pF
Table 26. SUB-LVDS CHARACTERISTICS
Parameter
Symbol
Minimum
Typical
Maximum
Unit
Differential Output Voltage
V
OD
140
180
220
mV
VOD Variation between Complementary Output States
D
V
OD
−5
−
5
mV
Common Mode Output Voltage
V
OCM
0.88
0.90
0.92
V
VOCM Variation between Complementary Output States
D
V
OCM
−10
−
10
mV
High Impedance Leakage Current
I
OZD
−1
−
1
m
A
Output Short Circuit Current:
When D+ or D− Connected to Ground
When D+ or D− Connected to 3.3 V
I
OSD
1.4
10.21
−
−
2.2
30.47
mA
Output Capacitance
C
DO
−
1.3
−
pF
Maximum Transmission Capacitance Load Expected
(for 260 MHz LVDS Clock)
−
−
10
pF
Table 27.
Parameter
Minimum
Typical
Maximum
Unit
LVDS_CLK
50
160
160
MHz
Duty Cycle on LVDS_CLK
−
50
−
%