KAC−12040
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31
SPI (SERIAL PERIPHERAL INTERFACE)
The SPI communication interface lets the application
system to control and configure the sensor. The sensor has
an embedded slave SPI interface. The application system is
the master of the SPI bus.
Table 22.
Name
Sensor I/O
Direction
Description
CSN
I
SPI Chip Select − Active low, this input activates the slave interface in the sensor.
SCK
I
SPI Clock − Toggled by the master.
MISO
O
SPI Master Serial Data Input − Slave (sensor) serial data output.
MOSI
I
SPI Master Serial Data Output − Slave (sensor) serial data input.
Table 23.
Parameter
Minimum
Typical
Maximum
Unit
SPI SCK
5
25
50
MHz
Duty Cycle on SPI SCK
40
50
60
%
Clock Polarity and Phase
CPOL (Clock POLarity) and CPHA (Clock PHAse) are
commonly defined in SPI protocol such as to define SCK
clock phase and polarity. The KAC−12040 defaults to
expecting the master to be configured with CPOL = 1
(the base value of the clock is VDD_DIG) and CPHA = 1
(data is valid on the clock rising edge).
Figure 22. CPOL = 1 and CPHA = 1 Configuration
CSN
SCK
MOSI
MISO
X
X
X
X
…
…
…
…
