ON Semiconductor Fairchild PFC SPM, Design Manual

Page: 15 / 19

PFC SPM
®
Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
14
DC-link Voltage Control
C
VF
R
VF
V
ref
EA
OUT
EA
-
Vdc
R
VS1
R
VL
R
VD
R
D1
R
D2
V
SIG
Outer
OP-AMP
R
VS2
Fig.10 DC link voltage control circuit
The relation between V
DC
and parameters is:
SIG
D D
D
VS
VL
EA
VS
VD VL
VL VD
VF VF
VD
VS VF VS VF
VD
VL DC
V
R R
R
R
R
V
R
R R
R R
R R
R
R R R R
R
R V














  








 






  
2 1
1
1 1 1 1
1
1
1 1
5 . 7
The variable V
DC
voltage is available by just changing V
SIG
voltage. V
EA
, the output of voltage error
amplifier changes from 0 to 5.5V as its load current. In no load condition, V
EA
value is almost zero. And the
voltage of V
DC
will be the highest value. The next graph shows V
SIG
and V
DC
voltage. The voltage of V
DC
in
low load condition is higher than that of max. load condition.
Fig.11. DC link voltage vs. control voltage
Min. load
Max. load
V
SIG
[V]
V
DC
[V]