ON Semiconductor Fairchild PFC SPM, Design Manual

Page: 10 / 19

PFC SPM
®
Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
9
R
i
C
p
C
z
R
z
IA
+
C A
O U T
IA
-
R
M O
Fig.4 Current loop circuit
Fig.5 Desired current error amplifier response
[1]
z i
dB
C fR
G

2
1
log 20

(Eq.6)
[2]
i
z
dB
R
R
G log 20

(Eq.7)
[3]
p i
dB
C fR
G

2
1
log 20

(Eq.8)
F
Z
=3.3kHz
F
C
=6.7kHz
F
P
=20kHz