ON Semiconductor Fairchild PFC SPM, Design Manual

Page: 11 / 19

PFC SPM
®
Design Guide
© 2005 Rev. 1.0.1-2012 Fairchild Semiconductor – System Engineering Group
10
Voltage Loop
f f V V sC
P
G
EAOUT OUTDC OUT
IN
L O V
419
5 380 001 . 0 2
5000
. . .

  




A resistor(R
VD
) is added between E/A input and sensing resistor. By virtue of large R
VD
, C
VF
can be
replaced by small SMD type capacitor.

 
k R
VD
120
(>R
VS
)
   
M R R
VD VF
1 8
(>R
VD
)
120
2
1
 
VF VD
CV
C R
f

 C
VF
=1uF
 
Hz f
CV
3 . 1

C
VF
R
VF
V
ref
E A
O U T
E A
-
Vdc
R
VS
R
VL
R
VD
Fig.6 Voltage loop circuit
Other Parameters
R
T
, C
T
: Switching frequency decision
T T
C R
f
6 . 0

R
T
= 15[k Ω ]
C
T
= 1[nF]
 F
s
= 40[kHz]
R
MO
: (Refer to fig.4)