Omnivision CameraChip OV9650, Implementation Manual

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Timing Generator
Version 1.1, December 7, 2004 Proprietary to OmniVision Technologies 11
O
mni ision
3.3 Frame Rate Timing
The OV9650 offers three methods of frame rate adjustment:
• Clock Prescalar (Timing Generator)
• Dummy Pixel Adjustment (Output Formatter)
• Dummy Line Adjustment
3.3.1 Clock Prescalar (Timing Generator)
OV9650 divides the input clock by 2 first. Setting register CLKRC [7] (0x11) high turns on the internal
clock doubler. Register CLKRC [5:0] is the internal clock pre-scalar. By programming register
CLKRC [5:0] (0x11), the frame rate and pixel rate can be divided by 1, 2, 3, 4, ... 64. The internal
clock frequency, f
INT CLK
, can be expressed as follows:
f
INT CLK
= f
CLK
×
(( CLKRC [7]
+
1) / 2) / ( CLKRC [5:0]
+
1)
t
INT CLK
= t
CLK
×
( CLKRC [5:0]
+
1) / (( CLKRC [7]
+
1) / 2)
Table 3-1 shows the maximum frame rate and pixel clock (PCLK) for the given input clock rate
(XCLK1). RGB raw pixel clock rate is half of YUV mode for the same frame rate and resolution.
Table 3-1. Frame Rate, Pixel Clock Rate, and Input Clock Rate ( CLKRC =0x81, 4X PLL)
Resolution/Mode Maximum Frame Rate (fps) XCLK1 (MHz) PCLK (MHz)
SXGA/Raw RGB 15 12 24
SXGA/YUV 15 12
a
a. CLKRC =0x80
48
VGA/Raw RGB 30 12 12
VGA/YUV 30 12 24
QVGA/Raw RGB 60 12 6
QVGA/YUV 60 12 12
QQVGA/Raw RGB 60 12 3
QQVGA/YUV 60 12 6
CIF/Raw RGB 60 12 12
CIF/YUV 60 12 24
QCIF/Raw RGB 120 12 6
QCIF/YUV 120 12 12
QQCIF/Raw RGB 120 12 3
QQCIF/YUV 120 12 6