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Proprietary to OmniVision Technologies
Version 1.1, December 7, 2004
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChip™
O
mni
ision
3.6 RGB Raw Data Output Sequence
Review the
OV9650 Datasheet
for complete details regarding the RGB raw data output. Register
[4] (0x15) determines when the data is valid. Setting register
[4] (0x15) t0 "1"
indicates the data is updated at the rising edge and valid at the falling edge of PCLK. Setting register
[4] (0x15) t0 "0" indicates the data is updated at the falling edge and valid at the rising edge
of PCLK. The data receiver should latch data when data is valid, with either the rising or falling edge
of PCLK, depending on register
[4] (0x15). Depending on this polarity selection, if the HREF
signal is high, the data is valid. If the HREF signal is low, the data is not valid. HREF polarity can
also be changed by setting register
[3] (0x15).
When using the HSYNC signal, adjust registers
(0x30), and
(0x31)
to adjust the HSYNC signal rising and falling edges to obtain valid data. To obtain the HSYNC and
HREF width, set registers
(0x17) and
(0x18) or
(0x30),
and
(0x31), respectively.
4 Analog Processing Block
This block performs all analog image functions including Automatic Gain Control (AGC), Automatic
White Balance (AWB), and other image manipulation functions
4.1 Gain Control
The OV9650 C
AMERA
C
HIP
provides support for both AGC and manual gain control modes.
4.1.1 Manual Gain Control
The manual gain control mode allows for the companion backend processor to control the OV9650
gain value. The companion backend processor may write gain control values to the C
AMERA
C
HIP
RGB raw data register
[7:0] (0x00) according to its corresponding AGC algorithm. The gain
value is shown in