Omnivision CameraChip OV9650, Implementation Manual

Page: 45 / 56

SCCB Interface
Version 1.1, December 7, 2004 Proprietary to OmniVision Technologies 45
O
mni ision
14 COM9 4A RW
Common Control 9
Bit[7]: Reserved
Bit[6:4]: Automatic Gain Ceiling - maximum AGC value
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: 64x
110: 128x
Bit[3]: Exposure timing can be less than limit of banding filter when
light is too strong
Bit[2]: Data format - VSYNC drop option
0: VSYNC always exists
1:
VSYNC will drop when frame data drops
Bit[1]: Enable drop frame when AEC step is larger than the
Exposure Gap
Bit[0]: Freeze AGC/AEC
15 COM10 00 RW
Common Control 10
Bit[7]: Set pin definition
1:
Set RESET to SLHS (slave mode horizontal sync) and
set PWDN to SLVS (slave mode vertical sync)
Bit[6]: HREF changes to HSYNC
Bit[5]: PCLK output option
0:
PCLK always output
1: No PCLK output when HREF is low
Bit[4]: PCLK reverse
Bit[3]: HREF reverse
Bit[2]: Reserved
Bit[1]: VSYNC negative
Bit[0]: HSYNC negative
16 RSVD 00 – Reserved
17 HSTART 1A RW
Output Format - Horizontal Frame (HREF column) start high 8-bit (low
3 bits are at
HREF [2:0])
18 HSTOP BA RW
Output Format - Horizontal Frame (HREF column) end high 8-bit (low
3 bits are at
HREF [5:3])
19 VSTRT 01 RW
Output Format - Vertical Frame (row) start high 8-bit (low 3 bits are at
VREF [2:0])
1A VSTOP 81 RW
Output Format - Vertical Frame (row) end high 8-bit (low 3 bits are at
VREF [5:3])
1B PSHFT 00 RW
Data Format - Pixel Delay Select (delays timing of the D[9:0] data relative
to HREF in pixel units)
• Range: [00] (no delay) to [FF] (256 pixel delay which accounts for
whole array)
1C MIDH 7F R Manufacturer ID Byte – High (Read only = 0x7F)
Table 10-2. Device Control Register List (Continued)
Address
(Hex)
Register
Name
Default
(Hex) R/W Description