Omnivision CameraChip OV9650, Implementation Manual

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44 Proprietary to OmniVision Technologies Version 1.1, December 7, 2004
OV9650 Color CMOS SXGA (1.3 MegaPixel) CameraChip™ O
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0F COM6 43 RW
Common Control 6
Bit[7]: Output of optical black line option
0:
Disable HREF at optical black
1: Enable HREF at optical black
Bit[6:4]: Reserved
Bit[3]:
Enable bias for ADBLC
Bit[2]: ADBLC offset
0:
Use 4-channel ADBLC
1: Use 2-channel ADBLC
Bit[1]: Reset all timing when format changes
Bit[0]: Enable ADBLC option
10 AECH 40 RW
Exposure Value
Bit[7:0]: AEC[9:2] (see registers AECHM for AEC[15:10] and COM1
for AEC[1:0])
11 CLKRC 00 RW
Data Format and Internal Clock
Bit[7]: Digital PLL option
0:
Disable double clock option, meaning the maximum
PCLK can be as high as half input clock
1: Enable double clock option, meaning the maximum
PCLK can be as high as input clock
Bit[6]: Use input clock directly (no clock pre-scale available)
Bit[5:0]: Internal clock pre-scalar
F(internal clock) = F(input clock)/(Bit[5:0]+1)
•
Range: [0 0000] to [1 1111]
12 COM7 00 RW
Common Control 7
Bit[7]: SCCB Register Reset
0:
No change
1: Resets all registers to default values
Bit[6]: Output format - VGA selection
Bit[5]: Output format - CIF selection
Bit[4]: Output format - QVGA selection
Bit[3]: Output format - QCIF selection
Bit[2]: Output format - RGB selection
Bit[1]: Reserved
Bit[0]: Output format - Raw RGB (COM7[2] must be set high)
13 COM8 8F RW
Common Control 8
Bit[7]: Enable fast AGC/AEC algorithm
Bit[6]: AEC - Step size limit (used only in fast condition and
COM5 [0] is low)
0: Fast condition change maximum step is VSYNC
1: Unlimited step size
Bit[5]: Banding filter ON/OFF
Bit[4:3]: Reserved
Bit[2]:
AGC Enable
Bit[1]: AWB Enable
Bit[0]: AEC Enable
Table 10-2. Device Control Register List (Continued)
Address
(Hex)
Register
Name
Default
(Hex) R/W Description