• It is recommended to send the PCB to the crystal manufacturer to determine the negative oscillation margin as well as the
optimum regarding C
XTAL
and C
EXTAL
capacitors. The data sheet includes recommendations for the tank capacitors C
XTAL
and C
EXTAL
. These values together with the expected PCB, pin, etc. stray capacity values should be used as a starting
point.
• Signal traces between the XTAL/EXTAL pins, the crystal and the external capacitors must be as short as possible, without
using any via. This minimizes parasitic capacitance and sensitivity to crosstalk and EMI. The capacitance of the signal
traces must be considered when dimensioning the load capacitors.
• In case there is only 1-2 PCB layers, it is recommended to place a guard ring around the oscillator components and to
connect it to the a solid ground plane. A ground area should be placed under the crystal oscillator area. This ground guard
ring must be clean ground. This means that no current from and to other devices should be flowing through the guard ring.
This guard ring should be connected to VSS x of the S32K1xx with a short trace. Never connect the ground guard ring to
any other ground signal on the board. Also avoid implementing ground loops.
• The main oscillation loop current is flowing between the crystal and the load capacitors. This signal path (crystal to C
EXTAL
to
CXTAL
to crystal) should be kept as short as possible and should have a symmetric layout. Hence, both capacitor’s
ground connections should always be as close together as possible.
• The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
The following figure 3, shows the recommended placement and routing for the oscillator layout.
Figure 3. Suggested crystal oscillator layout
5 Debug and programing interface
A number of commonly used debug connectors are shown here. Most of the ARM development tools uses one of these pin out’s.
When developing your ARM circuit board, it is recommended to use a standard debug signal arrangement to make connection
to debugger easier.
The SWD/SWV pins are overlaid on top of the JTAG pins as follows:
NXP Semiconductors
Debug and programing interface
Hardware Design Guidelines for S32K1xx Microcontrollers , Rev. 3, December 2018
Application Note
5 / 33
